Patent
1978-08-31
1980-03-18
Brown, Thomas W.
H04Q 354
Patent
active
041940903
ABSTRACT:
A decentralized control-type electronic switching system having at least one signal processor, at least one call processor and at least one switch processor is disclosed. The signal processor accommodates a plurality of communications lines for receiving, storing and analyzing a line signal and a register signal sent from the communication lines and transmits a line signal and a register signal to the communication lines and stores an idle or busy state of the communication lines. The call determines the signal processor which accommodates an outgoing line to be connected to an incoming line on the basis of a signal received from the signal processor via the incoming line. The switch processor stores an idle or a busy state of links in a switch network and responds to a request from another processor for seeking an idol path between two communication lines designated by the request. A common system bus carries out data transfer between the respective processors, and an oscillator generates the system clock pulses to be used for controlling the data transfer. Each of the processors includes a system clock counter for controlling a sequence of data transmission onto the system bus. The counter is set to an initial value upon starting of the switching system and is thereafter stepped in synchronism with the system clock pulses. An inhibit circuit is operable when one processor is ready to transfer data to another processor for inhibiting the feeding of system clock pulses to the system clock counters of the several processors.
REFERENCES:
patent: 3974343 (1976-08-01), Cheney et al.
patent: 4074072 (1978-02-01), Christensen et al.
Sato Shohei
Yabe Hideo
Brown Thomas W.
Nippon Electric Co. Ltd.
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