Debugging techniques in a multithreaded environment

Details Debugging techniques in a multithreaded environment Debugging techniques in a multithreaded environment

2005-01-25

2005-01-25

Zhen, Wei (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Testing or debugging

Reexamination Certificate

active

06848097

ABSTRACT:
A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint instruction does not need to be returned to its original location for single-step execution, executing a debugger nub for each target as part of the target task but using a nub task thread for the nub execution that is separate from the target task threads, providing immunity from breakpoints for specified threads such as the nub thread via specialized breakpoint handlers used by those threads, and virtualizing the debugger nub such that a shared root nub provides a uniform interface between the debugger and the target while specialized nubs provide differing functionality based on the type of target being debugged.

REFERENCES:
patent: 4819234 (1989-04-01), Huber
patent: 4872167 (1989-10-01), Maezawa et al.
patent: 5168554 (1992-12-01), Luke
patent: 5301325 (1994-04-01), Benson
patent: 5333280 (1994-07-01), Ishikawa et al.
patent: 5450575 (1995-09-01), Sites
patent: 5504932 (1996-04-01), Vassiliadis et al.
patent: 5533192 (1996-07-01), Hawley et al.
patent: 5548717 (1996-08-01), Wooldridge et al.
patent: 5557761 (1996-09-01), Chan
patent: 5564051 (1996-10-01), Halliwell et al.
patent: 5581764 (1996-12-01), Fitzgerald et al.
patent: 5594864 (1997-01-01), Trauben
patent: 5598560 (1997-01-01), Benson
patent: 5632032 (1997-05-01), Ault et al.
patent: 5652889 (1997-07-01), Sites
patent: 5712996 (1998-01-01), Schepers
patent: 5754855 (1998-05-01), Miller et al.
patent: 5768591 (1998-06-01), Robinson
patent: 5768592 (1998-06-01), Chang
patent: 5774721 (1998-06-01), Robinson
patent: 5787245 (1998-07-01), You et al.
patent: 5794046 (1998-08-01), Meier et al.
patent: 5805892 (1998-09-01), Nakajima
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5826265 (1998-10-01), Van Huben et al.
patent: 5867643 (1999-02-01), Sutton
patent: 5877766 (1999-03-01), Bates et al.
patent: 5887166 (1999-03-01), Mallick et al.
patent: 5901315 (1999-05-01), Edwards et al.
patent: 5903730 (1999-05-01), Asai et al.
patent: 5913925 (1999-06-01), Kahle et al.
patent: 5953530 (1999-09-01), Rishi et al.
patent: 5961639 (1999-10-01), Mallick et al.
patent: 5966539 (1999-10-01), Srivastava
patent: 5978902 (1999-11-01), Mann
patent: 6002872 (1999-12-01), Alexander, III et al.
patent: 6002879 (1999-12-01), Radigan et al.
patent: 6009269 (1999-12-01), Burrows et al.
patent: 6029005 (2000-02-01), Radigan
patent: 6049671 (2000-04-01), Slivka et al.
patent: 6058493 (2000-05-01), Talley
patent: 6059840 (2000-05-01), Click, Jr.
patent: 6072952 (2000-06-01), Janakiraman
patent: 6101524 (2000-08-01), Choi et al.
patent: 6112293 (2000-08-01), Witt
patent: 6151701 (2000-11-01), Humphreys et al.
patent: 6151704 (2000-11-01), Radigan
patent: 6158045 (2000-12-01), You
patent: 6167358 (2000-12-01), Othmeer et al.
patent: 6282701 (2001-08-01), Wygodny et al.
patent: 6480818 (2002-11-01), Alverson et al.
patent: 6658650 (2003-12-01), Bates
patent: 6681384 (2004-01-01), Bates et al.
patent: 19710252 (1998-02-01), None
patent: 0422945 (1991-04-01), None
patent: 0455966 (1991-11-01), None
patent: 0537098 (1993-04-01), None
patent: 0855648 (1998-07-01), None
patent: 0864979 (1998-09-01), None
patent: 2307760 (1997-06-01), None
Sistare et al. A Scalable Debugger for Massively Parallel Message-Passing Programs. IEEE. 1994. pp. 50-56.*
Keyes et al. Analysis of a Scheduler for a CAD Framework. ACM. 1999. pp. 152-161.*
Lumpp Jr. et al. CAPS: A coding AID for PASM. ACM. 1991. pp. 104-117.*
Wu et al. A New Framework for Debugging Globally Optimized Code. ACM. 1999. pp. 181-191.*
Smith, Burton, “The End of Architecture,” Keynote Address Presented at the 17thAnnual Symposium on Computer Architecture, Seattle, Washington, May 29, 1990.
Richard Korry et al., “Memory Management in the Tera MTA System,” 1995.
Gail Alverson et al., “Processor Management in the Tera MTA System,” 1995.
Major System Characteristics of the TERA MTA, 1995.
Touzeau, Roy F., “A Fortran Compiler for the FPS-164 Scientific Computer,” Proceedings of the ACM SIGPLAN '84 Symposium on Compiler Construction, SIGPLAN Notices 19(6):48-57, Jun. 1984.
Linton, Mark A., “The Evolution of Dbx,”USENIX Summer Conference, Jun. 11-15, 1990.
David Callahan and Burton Smith, A Future-Based Parallel Language for a General-Purpose Highly-Parallel Computer, Languages and Compilers for Parallel Computing, MIT Press, 1990.
David Callahan et al., “Improving Register Allocation for Subscripted Variables,” Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, White Plans, New York, Jun. 20-22, 1990.
Adelberg, Brad et al., “The Strip Rule System for Efficiently Maintaining Derived Data,” Sigmod Record, Association for Computing Machinery, New York, vol. 26, No. 2, Jun. 1, 1997.
Surajit, Chaudhuri and Umeshwar Dayal, “An Overview of Data Warehousing and OLAP Technology,” Sigmod Record, Association for Computing, New York, vol. 26, No. 1, Mar. 1997.
Agrawal, Gagan and Joel Saltz, “Interprocedural Data Flow Based Optimizations for Compilation of Irregular Problems,” Annual Workshop on Languages and Compilers for Parallel Computing, 1995.
Callahan, David, “Recognizing and Parallelizing Bounded Recurrences,” Aug. 1991.
D.H. Bailey et al., “The NAS Parallel Benchmarks—Summary and Preliminary Results,” Numerical Aerodynamic Simulation (NAS) Systems Division, NASA Ames Research Center, California, 1991.
Robert Alverson et al, “The Tera Computer System,”Proceedings of 1990 ACM International Conference on Supercomputing, Jun. 1990.
Gail Alverson et al., “Scheduling on the Tera MTA,” Job Scheduling Strategies for Parallel Processing, 1995.
Briggs, Preston and Keith D. Cooper, “Effective Partial Redundancy Elimination,” ACM SIGPLAN Notices, Association for Computing Machinery, New York, vol. 29, No. 6, Jun. 1 1994.
Click, Cliff, “Global Code Motion, Global Value Numbering,” ACM SIGPLAN Notices, Assocation for Computing Machinery, New York, vol. 30, No. 6, Jun. 1, 1995.
Sreedhar, Vugranam C. and Guang R. Gao, “Incremental Computation of Dominator Trees,” ACM SIGPLAN Notices, Association for Computing Machinery, New York, vol. 30, No. 3, Mar. 1, 1995.
Galarowicz, Jim et al., “Analyzing Message Passing Programs on the Cray T3E with PAT and VAMPIR,” Research Report, “Online!”, May 1998.
Anderson, Jennifer, et al., “Continuous Profiling: Where Have All The Cycles Gone?,” Operating Systems Review, ACM Headquarters, New York, vol. 31, No. 5, Dec. 1, 1997.
Smith, Burton, “Opportunities for Growth in High Performance Computing,” Nov. 1994.
Goldman, Kenneth, J., “Introduction to Data Structures,” 1996, Retrieved from Internet http://www.cs.wustl.edu/{kjg/CS101_SP97/Notes?DataStructures/structures.html.
A. Ram., et al., “Parallel Garbage Collection Without Synchronization Overhead,” 12thAnnual Symposium on Computer Architecture, Jun. 17, 1985.
H. Hayashi et al., “ALPHA: A High Performance Lisp Machine Equipped with a New Stack Structure and Garbage Collection System,” 10thAnnual International Symposium on Computer Architecture, 1983.
Jack W. Davidson and David B. Whalley, “Reducing the Cost of Branches by Using Registers,” Proceedings of the 17thAnnual Symposium on Computer Architecture, Seattle, Washington, May 28-31, 1990.
Jens Knoop et al., “The Power of Assignment Motion,” ACM SIGPLAN '95 Conference on Programming Language Design and Implementation, La Jolla, California, Jun. 18-21, 1995.
Hiralal Agrawal, “Dominators, Super Blocks, and Program Coverage,” 21stACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Portland, Oregon, Jan. 17-21, 1

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