Debugging system using virtual storage means, a normal bus cycle

Details Debugging system using virtual storage means, a normal bus cycle Debugging system using virtual storage means, a normal bus cycle

1994-04-05

1997-03-04

Nguyen, Hoa T.

39518301, 39518319, G06F 1130

Patent

active

056088671

ABSTRACT:
A debugging system is adapted to perform debugging by employing a virtual address in a computer system which includes a microprocessor incorporating a virtual storage function and a function for outputting a normal bus cycle corresponding to a real address in a normal operation and a function for outputting a debugging bus cycle corresponding to a virtual address. The microprocessor outputs a signal indicative of a kind of access and a signal indicative of an outputting state of a virtual address during outputting of the virtual address in the debugging bus cycle. A memory device is connected to the microprocessor through an address bus and a data bus. The debugging system includes a bus monitoring means for monitoring output of the processor, the output from bus cycles and transfer data. The bus monitoring means includes a debugging means for performing the debugging process associated with the virtual address.

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