1997-09-03
1999-07-27
Beausoliel, Jr., Robert W.
39518305, 395701, 395704, G06F 1126
Patent
active
059304707
ABSTRACT:
A target CPU executes a user program in synchronism with an asynchronous operation clock signal at higher speed than an operation clock signal of a debugging object system. A control unit portion outputs address bus information, data bus information, and machine cycle information in operation. A POD portion generates various control signals of the debugging object system based on the machine cycle information and then the address bus information, the data bus information, and the machine cycle information to the debugging object system in synchronism with an operation clock signal of the debugging object system. Collection, output, or process of debugging information can thus be executed by use of difference in execution times of the user program between the debugging object system and the target CPU, without halting the debugging object system.
REFERENCES:
patent: 5047926 (1991-09-01), Kuo et al.
Kawakita Hideyuki
Noguchi Tomoaki
Baderman Scott T.
Beausoliel, Jr. Robert W.
Kabushiki Kaisha Toshiba
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