Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1999-01-07
2001-09-04
Dam, Tuan Q. (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S152000, C714S035000, C345S215000
Reexamination Certificate
active
06286132
ABSTRACT:
This application is based on an application Ser. No. 10-1407 filed in Japan, the content of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a debugging support apparatus that supports operation verification for a long word instruction sequence, a parallel execution information generation device that is included in a compiler and used by a debugging support apparatus, a computer-readable recording medium storing a debugging support program, and a computer-readable recording medium storing a parallel execution information generation program.
2. Description of the Background Art
In recent years, parallel execution methods have been widely used in the development of microprocessors. Parallel execution means to execute a plurality of instructions in parallel in one machine cycle, and is typically achieved by superscalar methods and VLIW (Very Long Instruction Word) methods.
With superscalar methods, dedicated circuits inside the processor dynamically analyze instructions that can be executed in parallel,.and then these instructions are separately executed by a plurality of instruction execution units.
Superscalar methods have an advantage of being compatible with serial execution methods. That is, a processor that uses a superscalar method can execute object code that a compiler generates for a processor that uses a serial execution method. On the other hand, superscalar methods have a disadvantage in that a processor needs to includes the dedicated hardware used to analyze the instructions that are executed in parallel, which results in increasing hardware costs.
With VLIW methods, the word length of the processor is set based on an integral multiple of the word length of instructions generated as object code. In this specification, an instruction indicated by object code is called an object code instruction to distinguish it from a VLIW instruction. One VLIW instruction includes a plurality of object code instructions that can be executed in parallel, and these object code instructions are separately executed by a plurality of instruction execution units. Here, the processing that analyzes which object code instructions can be executed in parallel and inserts object code instructions into VLIW instructions is called scheduling.
With VLIW methods, the processor does not need to judge it a group of instructions can be executed in parallel when executing the instructions, so that hardware reduction can be made. However, when all the storage areas in one VLIW instruction can't be filled with object code instructions, as often happens, nop code instructions are inserted into the areas where no object code instruction is placed, This has a drawback in that the total code size increases by the size of the inserted nop code instructions, which in turn leads to an increase in memory size.
Such a disadvantage, however, can be reduced by improving the method for inserting object code instructions into VLIW instructions so that less nop code instructions are used. Therefore, in terms of reducing hardware costs, the VLIW method can be considered more promising.
With the VLIW method, a compiler performs the scheduling. This means that the compiler determines which object code instructions should be placed into each VLIW instruction. As the analysis of parallelism and scheduling of object code instructions by compilers becomes increasingly advanced, the resulting VLIW instruction sequence is becoming increasingly removed from the source program written by a programmer.
As a result, when a programmer runs a VLIW instruction sequence on a target machine, it is difficult for the programmer to grasp the correspondence between the object code instructions that are executed in parallel by the VLIW processor and the source code instructions in the programmer's source program. Programmers are often unable to understand which group of source code instructions are being executed in parallel. Accordingly, when an error is detected during operation verification, the programmer can have problems in ascertaining which source code instruction in a source program caused the error. This leads to the problem of debugging taking a long time.
High-level language-oriented developments, where every development stage from the program coding to operation verification on the target appliance is performed using a high-level language, have been subject to increasing attention. Since VLIW instructions are written in object code, however, the programmer may be unable to ascertain which source code instruction in a source program is the cause of an error. In this case, the programmer has to correct the error by directly rewriting the code in the VLIW instructions, such as by applying a patch. This means that the benefits of a high-level language-oriented development environment cannot be obtained.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a debugging support apparatus and a parallel execution information generation device with which the user can find a cause of an error at the source program level during operation verification for a VLIW sequence, even when a significant gap exists between the source program written by a programmer and the VLIW instruction sequence produced from the source program.
The above object can be achieved by the debugging support apparatus of claim
1
.
According to claim
1
, the debugging support apparatus supports operation verification by a user for a long word instruction sequence containing at least one long word instruction, including: a first storage unit for storing sets of parallel execution information that each contain a long word instruction address and a group of line numbers that each specify a source code statement in a source program, wherein source code statements specified by the group of line numbers can be executed in parallel and have been placed into the long word instruction after being translated into object code; a reception unit for receiving from a user an operation verification command that designates a line number specifying a source code statement; a reading unit for reading, when a set of parallel execution information that contains the designated line number exists, the set of parallel execution information from the first storage unit; and a display unit for visually indicating at least one source code statement specified by a line number in the read set of parallel execution information aside from the designated line number.
As a result, even when a significant gap exists between the source program written by a programmer and a VLIW instruction sequence converted from the source program, the programmer can soon understand which source code statements are executed in parallel. Accordingly, debugging can be performed more efficiently when an error is detected in a VLIW instruction sequence during operation verification, since the programmer can easily detect the source code statement that causes the error.
Here, the display unit may include: a first list display unit for displaying a first program list that contains the source code statement specified by the designated line number; a second list display unit for displaying a second program list that contains a source code statement specified by a line number in the read set of parallel execution information aside from the designated line number; and a modification unit for modifying a display by the second list display unit of the source code statement that is specified by the line number in the read set of parallel execution information.
Accordingly, a programmer is made aware of which source code statements are being performed in parallel, and can perform the debugging more efficiently when an error is detected in a VLIW instruction sequence during operation verification, as the programmer can easily detect the source code statement that causes the error.
Consequently, even when object code instructions generated by the compiler are inserted into a VLIW instruction sequence, a “high-level la
Odani Kensuke
Sumi Fumio
Tanaka Akira
Tanaka Hirohisa
Dam Tuan Q.
Matsushita Electric - Industrial Co., Ltd.
Price and Gess
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