Debugging microprocessor

Details Debugging microprocessor Debugging microprocessor

1987-10-29

1989-11-14

Fleming, Michael R.

Excavating

371 291, 364900, 3649449, G06F 1100

Patent

active

048812285

ABSTRACT:
A debugging processor includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, and an interrupt control unit for notifying the instruction execution unit of an interrupt request. The debugging processor also comprises a debug interrupt response control unit having a priority higher than that of the interrupt control unit and having a fixed branch destination address. This debug interrupt response control unit operates to generate to the external a debug interrupt response signal which becomes active during a period of save operation for an internal information.

REFERENCES:
patent: 3937938 (1976-02-01), Matthews
patent: 3987420 (1976-10-01), Badagnami
patent: 4308581 (1981-12-01), Raghunathan
patent: 4410938 (1983-10-01), Higashiyama
patent: 4635193 (1987-01-01), Moyer
patent: 4755997 (1988-07-01), Takahashi

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