Debugging a processor using data output during idle bus cycles

Details Debugging a processor using data output during idle bus cycles Debugging a processor using data output during idle bus cycles

1996-02-27

1998-11-17

Canney, Vincent P.

G06F 1100

Patent

active

058388974

ABSTRACT:
A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.

REFERENCES:
patent: 4479178 (1984-10-01), Schabowski
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5544311 (1996-08-01), Harenberg et al.

Affiliated with

Also associated with

Rating

Debugging a processor using data output during idle bus cycles does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Debugging a processor using data output during idle bus cycles, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Debugging a processor using data output during idle bus cycles will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-894148