Patent
1996-11-14
1998-09-22
Heckler, Thomas M.
395557, 39518301, G06F 1100
Patent
active
058128301
ABSTRACT:
Disclosed herein is sophisticated but low-cost debug hardware which may be used to identify the root cause of a functional or electrical problem in a microprocessor chip. The debug system comprises a raw mode trigger capability which allows microprocessor events to be generated either synchronously or asynchronously to a clock which steps an instruction pipeline. The debug system comprises one or more trigger means, one or more event generation means, and programmable means for alternately placing the one or more trigger means in synchronous or asynchronous mode. Each of the trigger means is implemented internally to a microprocessor so as to sample microprocessor signals and generate a number of triggers as programmed values of the microprocessor signals are detected. Each of the event generation means is also implemented internally to a microprocessor, and may be used to generate one or more microprocessor events in response to programmed combinations of the number of triggers generated by said trigger means. If desired, generation of a microprocessor event may be delayed until either 1) a programmed trigger combination has occurred a set number of times, or 2) a programmable countdown timer has expired.
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U.S. application No. 08/711,491 of Gregory L. Ranson, et al. filed Sep. 10, 1996 for: On-Chip Debug Support and Performance Monitoring in a Microprocessor.
Naaseh-Shahry Hosein
Tobin Paul G.
Heckler Thomas M.
Hewlett--Packard Company
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