Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1998-03-04
2001-02-13
Hafiz, Tariq R. (Department: 2762)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C712S227000, C714S034000, C714S038110
Reexamination Certificate
active
06189140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems such as microprocessors. More specifically, the present invention relates to a software debug support system and operating method in processors.
2. Description of the Related Art
The growth in software complexity, in combination with increasing processor clock speeds, has placed an increasing burden on application software developers. The cost of developing and debugging new software products is now a significant factor in processor selection. A failure to include adequate software debug functionality in a processor results in longer customer development times and reduces attractiveness of the processor for use within industry. Software debug support is particularly useful in the embedded products industry, where specialized on-chip circuitry is often combined with a processor core.
The software debug tool configuration of a processor addresses the needs of several parties in addition to the software engineer who develops program code for execution on the processor. A “trace” algorithm developer searches through captured software trace data that reflects instruction execution flow in a processor. An in-circuit emulator developer deals with problems of signal synchronization, clock frequency and trace bandwidth. A processor manufacturer seeks a software debug tool solution that avoids an increased processor cost or design and development complexity.
In the desktop systems, complex multitasking operating systems are currently available to support software debugging. However, the initial task of getting the operating systems running reliably often calls for special development equipment. While not standard in the desktop environment, development equipment such as logic analyzers, read-only memory (ROM) emulators, and in-circuit emulators (ICE) are sometimes used in the embedded industry. In-circuit emulators have some advantages over other debug environments including complete control and visibility over memory and register contents, and supplying overlay and trace memory if system memory is insufficient.
Traditional in-circuit emulators are used by interfacing a custom emulator back-end with a processor socket to allow communication between emulation equipment and the target system. The custom design of emulator interfaces in increasingly unrealistic and expensive as product life cycles are reduced and nonstandard and exotic integrated circuit packages are predominant in present day processor design.
Few known processor manufacturing techniques are available that include a suitable full-function in-circuit emulation functionality. Most processors in personal computer (PC) systems implement emulation functionality using a multiplexed approach in which existing pins are multiplexed for alternative use in a software debug application. Multiplexing of pins is not desirable in embedded controllers, which inherently suffer from overload of pin functionality.
Some advanced processors multiplex debug pins in time, for example by using the address bus to report software trace information during a Branch Target Address (BTA) cycle. The BTA-cycle is stolen from regular bus operation cycles. However in debug environments with high branch activity and low cache hit rates, BTA-cycles are often fully occupied handling branches, resulting in a conflict over access to the address bus that necessitates processor “throttle back” to prevent a loss of instruction race information. For example, software in the communications industry is branch-intensive and suffers poor cache utilization often resulting in 20% or more throttle back, an unacceptable amount for embedded products which are subject to real-time constraints.
In another approach, a second “trace” or “slave” processor is combined with a main processor, with the two processors operating in-step. Only the main processor fetches instructions. The second, slave processor monitors fetched instructions on the data bus and maintains an internal state in synchronization with the main processor. The address bus of the slave processor supplies trace information. After power-up, via a JTAG (Joint Test Action Group) input, the second processor is switched into a slave mode of operation. The slave processor, freed from instruction fetch duties, uses the slave processor address bus and other pins to supply trace information.
Another existing debug strategy utilizes implementation of debug support into every processor in a system, but only bonding-out signal pins in a limited number of packages. The bond-out versions of the processor are used during debug and replaced with the smaller package for final production. The bond-out approach suffers from the need to support additional bond pad sites in all fabricated devices, a burden in small packages and pad limited designs, particularly if a substantial number of extra pins are required by the debug support variant. Furthermore, the debug capability of specially-packaged processors is unavailable in typical processor-based production systems.
In yet another approach, specifically the Background Debug Mode (BDM) implemented by Motorola, Inc., limited on-chip debug circuitry is implemented for basic run control. The BDM approach utilizes a dedicated serial link having additional pins and allows a debugger to start and stop the target system and apply basic code breakpoints by inserting special instructions in system memory. Once halted, special commands are used to inspect memory variables and register contents. The BDM system includes trace support, but not conveniently using the serial link. Instead the BDM system supplies trace support through additional dedicated pins and expensive external trace capture hardware that transfer instruction trace data.
Accordingly, present day techniques for software debugging suffer from a variety of limitations including increased packaging and development costs, circuit complexity, processor throttling, and bandwidth matching difficulties. Furthermore, no adequate low-cost procedure for providing trace information is currently available. The limitations of the existing solutions are likely to be exacerbated in the future as internal processor clock frequencies continue to increase.
What is needed is a software debug system and operating procedure that includes an improved trace capability.
SUMMARY OF THE INVENTION
A system for debugging a processor includes a debug interface including a handshake logic for communicating commands and data from a serial input/output port to a processor and to a trace control logic with a low delay. The handshake logic results in a low latency through the inclusion of a state machine that operates at the same speed as the processor. The state machine generates handshake signals to communicate among the serial input/output port, the processor, and the trace control logic.
In accordance with an embodiment of the present invention, a processor includes a debug interface for interfacing to an external debug device. The processor includes a processor core, a serial input/output port connected to the processor core and communicating information between the external debug device and the processor core, a trace logic accessing trace information indicating instruction execution flow in the processor core, and a debug interface. The debug interface is connected to the processor core, the serial input/output port, and the parallel input/output port. The debug interface includes a handshake logic generating handshake signals controlling communications between the serial input/output port and the processor core and between the trace logic and the processor core. The handshake logic includes a synchronization block synchronizing the handshake signals.
In accordance with another embodiment of the present invention, a debug interface for interfacing a processor to a debug device includes a serial input/output port, a trace logic connected to the serial input/output port, and an interface logic. The interface logic is connected to the serial input/output
Advanced Micro Devices , Inc.
Booker Kelvin E.
Hafiz Tariq R.
Zagorin O'Brien & Graham LLP
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