Debug interface for an event timer apparatus

Details Debug interface for an event timer apparatus Debug interface for an event timer apparatus

2005-01-04

2005-01-04

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system

Time duration or rate

C700S013000

Reexamination Certificate

active

06839654

ABSTRACT:
An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.

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