Debug bi-phase export and data recovery

Details Debug bi-phase export and data recovery Debug bi-phase export and data recovery

2005-03-15

2005-03-15

Frejd, Russell (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

Of peripheral device

C331S018000, C713S500000

Reexamination Certificate

active

06868376

ABSTRACT:
An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an operation circuit operating in synchronism with the function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. The trace data is sensed in synchronism with the oscillator clock. The emulator is coupled to the target device to control the clock selection. Accordingly, the trace export can operate at a frequency independent of the operation circuit.

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