Deadlock resolution with cache snooping

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Details

3642427, 3642434, 3649401, 3649642, G06F 1314, G06F 1336

Patent

active

051330741

ABSTRACT:
A device for resolving deadlock between a local processor and system resources for access to a local store in a multiprocessor data processing system having high speed cache comprises an address storage device, deadlock resolution logic and a deadlock detector. The address storage device is coupled to the local bus for storing addresses in response a local store access signal on the system bus and for supply of the address to the cache controller. The detector is connected to the local bus and system bus to detect a deadlock condition. The deadlock resolution logic generates a sequence of control signals in response to the deadlock signal that resolves the deadlock condition. In particular, deadlocks are resolved by tristating the local buffer in response to the deadlock signal to disable external access signals from controlling the local bus to allow a local store access signal to gain control of the local bus. If the local store access signal is a write access, the address of the write access is stored in the address store, and the local buffer is released from the high impedance state of allow the external access signal to control the local bus. After the external access signal completes, the address for the address store is supplied to the cache controller for performance of snooping function. If the local store access signal is a read access, then the local buffer is released from its high impedance state after the read access completes.

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patent: 4791554 (1988-12-01), Hirota et al.

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