Deadlock avoidance mechanism and method for multiple bus topolog

Details Deadlock avoidance mechanism and method for multiple bus topolog Deadlock avoidance mechanism and method for multiple bus topolog

1996-10-21

1998-02-10

Treat, William M.

Multiplex communications

Wide area network

Packet switching

395842, 370402, G06F 1328

Patent

active

057178739

ABSTRACT:
Apparatus and a method for eliminating deadlock in a multibus computer system which system includes a primary bus, and a secondary bus, a bridge circuit for joining the primary bus to a bus master, and a second bridge circuit for joining the primary bus to the secondary bus. The invention causes the second bridge circuit to generate a first signal directed to the all bridge circuits to indicate that a bus master on the secondary bus desires access to the secondary bus. All bridge circuits holding data directed to a component on the secondary bus flushes all temporary storage means holding data directed to a component on the secondary bus. The bridge circuits then generate signals to indicate that flushing is complete and the bus master on the secondary bus is granted access to the secondary bus. In one embodiment, the second bridge tests to determine whether the bus master requesting access requires a guaranteed access time and generates a signal to flush temporary storage in the first bridge between memory and the bridge.

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