Deadlock avoidance for switched interconnect bus systems

Details Deadlock avoidance for switched interconnect bus systems Deadlock avoidance for switched interconnect bus systems

1996-08-07

1997-10-28

Harvey, Jack B.

395290, 395310, 395312, G06F 1300

Patent

active

056824858

ABSTRACT:
A deadlock avoidance system for avoiding interconnection deadlocks between a plurality of data transfer devices includes a controller, a switch interconnector coupled to all of said data transfer devices for interconnecting on a one-to-one basis selected ones of the data transfer device as requesting units to selected ones of said data transfer devices as receiving units. A transfer queue is employed that includes a master transfer register and a slave transfer register, a master register, a slave register and a target register.

REFERENCES:
patent: 4494193 (1985-01-01), Brahm et al.
patent: 5081575 (1992-01-01), Hiller et al.
patent: 5175837 (1992-12-01), Arnold et al.
patent: 5179669 (1993-01-01), Peters

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