Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2001-01-16
2004-06-08
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S372000, C711S157000
Reexamination Certificate
active
06748033
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a de-interleave circuit used for a BS digital broadcasting receiver.
BACKGROUND ART
As is already known, an interleave system in a BS digital broadcasting receiver performs block interleave, 8×203 bytes in terms of bytes, interleaving between slots with a same slot number in each frame in the superframe direction.
Here, an MPEG2-TS bucket of a main signal of a BS digital broadcasting signal comprises 1 slot made up of 204 bytes, 203 bytes including parity 16 bytes for correction of external code errors plus 1 byte of a TMCC (Transmission and Multiplexing Configuration Control) signal to indicate a synchronization signal, modulation system and error correction system, etc., with 48 slots forming 1 frame and 8 frames forming 1 superframe.
De-interleaving data interleaved as shown above requires a memory with a storage capacity for 2 superframes. This requires a memory with a storage capacity of a maximum of 155904 bytes (=203 (bytes)×48 (slots)×8 frames×2 (superframes)).
However, configuring a conventional de-interleave circuit using a memory with a storage capacity amounting to 2 superframes involves such a problem that the number of gates increases when the de-interleave circuit is implemented with an integrated circuit and at the same time the chip area increases.
It is an object of the present invention to provide a de-interleave circuit that requires less memory.
DISCLOSURE OF THE INVENTION
The de-interleave circuit according to the present invention is a de-interleave circuit in a BS digital broadcasting receiver provided with address data generating means that generates address data A, in which assuming that the number of main signals in 1 slot is m, the depth of de-interleave is n, a specific address number assigned to a de-interleave memory is y, address data that specifies a data read/write address location is A, a modulo b is a remainder of a−&agr;b (&agr;: a natural number including 0),
when (y≠n×m−1), A=y×n to the xth power modulo (n×m−1), and
when (y=n×m−1), A=y,
address set number x, which is the number of times data of up to address number y is repeatedly specified, is such an x that when y=1, A=1 in A=y×n to the xth power modulo (n×m−1) and
when the value of y×n to the xth power is less than (n×m−1), A=(y×n to the xth power), and is characterized in that the main signal stored in the address location in a memory specified by the address data generated by the address generating means is read and the following main signal, which is interleaved and input, is written in that address location.
In the de-interleave circuit according to the present invention, the main signal stored in the address location in memory specified by address data A generated by the address generating means is read. Since the following main signal, which is interleaved and input, is written in the address location, which has been substantially emptied by the aforementioned read, de-interleave can be performed with a storage capacity for a de-interleave memory and the de-interleave memory requires a storage capacity only ½ of the conventionally required storage capacity of 2 superframes, which means that the required area is reduced when the circuit is implemented with an integrated circuit.
In the de-interleave circuit according to the present invention, the address data generating means is provided with:
a base-m counter that counts the number of main signals input;
a base-S counter that counts a carry of the base-m counter;
a multiplier that multiplies the count value of the base-S counter by (n×m);
offset value counting means that counts the number of main signals in the slot direction, shifts by one stage in the n direction when the main signal count value reaches (m−1) and counts main signals in the slot direction, and continues to count by repeating this procedure until the count value reaches (n×m); and
adding means that adds up the output of the multiplier and the count value of the offset value counting means, and is characterized in that the output of the adding means is deemed as address data A.
De-interleave is performed by reading a main signal from the address location in a memory specified by the address data output from the address generating means and writing the main signal.
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International Search Report.
Horii Akihiro
Shinjo Soichi
Shiraishi Kenichi
Bocure Tesfaldet
Kabushiki Kaisha Kenwood
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
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