De-glitchablenon-metastable flip-flop circuit

Details De-glitchablenon-metastable flip-flop circuit De-glitchablenon-metastable flip-flop circuit

1976-11-29

1978-06-06

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307247R, 328195, 328196, 328206, H03K 3286

Patent

active

040938786

ABSTRACT:
The flip-flop circuit of the present invention is one that cannot glitch or enter a metastable hang-up state and has a probability of one of being completely settled at some given finite time following clocking. The flip-flop circuit is comprised of an input logic gate, an integrator and a logic latch circuit. In operation, the input logic gate changes state upon the coincidence of input signals, which change in state causes the integrator to change output level at a controlled rate. The latch circuit is sensitive to the output level of the integrator and changes state only when the integrator's output level reaches or exceeds preselected thresholds.

REFERENCES:
patent: 3953744 (1976-04-01), Kawagoe
patent: 3983496 (1976-09-01), Bedford et al.

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