DDR interface for reducing SSO/SSI noise

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

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C375S375000, C713S500000

Reexamination Certificate

active

07486702

ABSTRACT:
An improved DDR interface uses single-ended technology and phase-shifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate. A dynamic phase adjustment circuit on the receiver compensates for the phase differences. Clock jitter and skew is reduced and the number of IDDQ pins is reduced to provide a more effective design and high density package.

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Optical Internetworking Forum, “System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices”, Implementation Agreement OIF-SPI4-02.0, Jan. 2001, 64 pages, The Optical Internetworking Forum, 39355 California Street, Suite 307, Fremont, CA 94538: <URL:http://www.oiforum.com/public/documents/OIF-SPI4-02.0.pdf>.

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