DCT/IDCT processor and data processing method

Details DCT/IDCT processor and data processing method DCT/IDCT processor and data processing method

1992-03-20

1993-09-28

Malzahn, David H.

Boots, shoes, and leggings

G06F 15332

Patent

active

052491463

ABSTRACT:
A one-dimensional discrete cosine transform processor of N (N: positive integer)-term input data X includes a preprocessing section for carrying out addition and subtraction of (i)th-term data x (i) and (N-i)th-term data x (N-1) of input data X, and a unit for performing a product sum operation for sets of intermediate data subjected to preprocessing by addition and sets of intermediate data subjected to preprocessing by subtraction, respectively. The product sum operation unit includes a data rearranging unit for outputting, in parallel and in order, bit data of the same figure of a set of data, a partial sum generator for generating a partial sum by using the parallel bit data as an address, and an accumulator for accumulating outputs of the partial sum generator. A one-dimensional inverse discrete cosine transform processor of N-term input data X includes a unit for performing a product sum operation of input data, and a postprocessing section for carrying out addition and subtraction of 2-term data in a predetermined combination of an output of the product sum operation unit. The number of times of multiplication is reduced by utilizing inherent characteristics of coefficients of DCT/IDCT processing. Since the product sum operation is performed by a ROM table and an adder, a faster multiplication is realized.

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"A 30 NS (600 MOPS) Image Processor with a Reconfigurable Pipeline Architecture", IEEE 1989 Custom Integrated Circuits Conference, by Kunitoshi Aono et al, 1989, pp. 24.4.1 to 24.4.4.

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