DCFL latch having a shared load

Details DCFL latch having a shared load DCFL latch having a shared load

1990-04-30

1991-10-08

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072121, H03K 326

Patent

active

050557092

ABSTRACT:
A DCFL latch circuit having minimum power and device count, comprising a first field-effect transistor having a drain, a gate coupled to a first input at which a data signal is supplied, and a source. A second field-effect transistor having a drain coupled to the source of the first field-effect transistor, a gate coupled to a second input at which a logic clock signal is supplied, and a source coupled to a first supply voltage terminal. A third field-effect transistor having a drain coupled to an output of the latch circuit, a gate coupled to the drain of the first field-effect transistor, and a source coupled to the first supply voltage terminal. A fourth field-effect transistor having a drain coupled to the drain of the first field-effect transistor, a gate coupled to the output, and a source. A fifth field-effect transistor having a drain coupled to the source of the fourth field-effect transistor, a gate coupled to a third input at which the inversion of the logic clock signal is supplied, and a source coupled to the first supply voltage terminal. A load circuit coupled to the drain of the third field-effect transistor for providing current thereto and a shared load circuit coupled to the drains of the first and fourth field-effect transistors for providing current to the first field-effect transistor when the clock signal is in a first logic state and for providing current to the fourth field-effect transistor when the clock signal is in a second logic state.

REFERENCES:
patent: 4629911 (1986-12-01), Berbernes et al.
patent: 4843264 (1989-06-01), Galbraith
patent: 4970406 (1990-11-01), Fitzpatrick
patent: 4978870 (1990-12-01), Chen et al.
patent: 4990799 (1991-02-01), Weiss

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