DC-to-DC converter

Details DC-to-DC converter DC-to-DC converter

2003-05-01

2004-12-14

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S272000

Reexamination Certificate

active

06831448

ABSTRACT:

The present invention relates to a DC-to-DC converter which receives a DC voltage from a battery or the like and supplies a controlled DC voltage to a load, and more particularly to a DC-to-DC converter capable of carrying out voltage step-up and step-down operation in an input-output noninverting manner in which the polarity of the input voltage is the same as that of the output voltage.
BACKGROUND OF THE INVENTION
A DC-to-DC converter which receives a DC voltage from a battery or the like and supplies a DC voltage obtained by voltage step-up or step-down operation in an input-output noninverting manner is disclosed in the Japanese Publication of examined patent application No. Sho 58-40913.
FIG. 13
is the circuit diagram of the DC-to-DC converter disclosed in the Japanese Publication of examined patent application No. Sho 58-40913.
FIG. 14
a
to
FIG. 14
d
are waveform diagrams showing the operation of the DC-to-DC converter.
In the DC-to-DC converter shown in
FIG. 13
, the cathode of a first diode
3
is connected via a first switch
2
to the positive pole
1
A of a DC input power source
1
generating a DC voltage Ei. The anode of the diode
3
is connected to the negative pole
1
B of the DC input power source
1
. One terminal of a second switch
5
is connected to the cathode of the diode
3
via an inductor
4
. The other terminal of the second switch
5
is connected to the negative pole
1
B. The switches
2
and
5
are formed of switches capable of turning on and turning off at a high frequency, such as a semiconductor switch. The anode of a second diode
6
is connected to the connection point of the inductor
4
and the switch
5
, and its cathode is connected to the negative pole
1
B via an output capacitor
7
. A load
8
is connected in parallel with the output capacitor
7
, and a DC output voltage Eo across both the terminals of the output capacitor
7
is applied to the load
8
. As shown in
FIG. 14
a
and
FIG. 14
b
, the first switch
2
and the second switch
5
turn on and turn off in the same constant switching period T. The ratio of the ON time period of the switch
2
to one switching period T is designated by &dgr;1, which is a duty ratio in the switch
2
. The ratio of the ON time period of the switch
5
to one switching period T is designated by &dgr;
2
, which is a duty ratio in the switch
5
. The duty ratio &dgr;
1
is made larger than the duty ratio &dgr;
2
as shown in the figures. The ratio of the ON time period is referred to as a duty ratio when represented by percentage. For convenience in explanation, it is assumed that the diodes
3
and
6
have no forward voltage drops in the conductive states.
When both the switch
2
and the switch
5
are in ON-state, the voltage Ei of the DC input power source
1
is applied to the inductor
4
. The time period of this voltage application is represented by &dgr;
2
·T as shown in
FIG. 14
b
. At this time, current flows from the DC input power source
1
to the inductor
4
, whereby magnetic energy is stored. Subsequently, when the switch
5
turns OFF, the diode
6
becomes conductive (turns ON) as shown in
FIG. 14
d
, and the voltage difference (Ei−Eo) between the DC input voltage Ei and the DC output voltage Eo is applied to the inductor
4
. The time period of this voltage application is represented by (&dgr;
1
−&dgr;
2
)·T. During this application time period, current flows from the DC input power source
1
to the output capacitor
7
via the inductor
4
. Then, when the switch
2
turns OFF, the diode
3
turns ON as shown in
FIG. 14
c
, and the DC output voltage Eo is applied to the inductor
4
in the inverse direction. The time period of this voltage application is represented by (
1
−&dgr;
1
)·T. During this application time period, current flows from the inductor
4
to the output capacitor
7
, whereby the stored magnetic energy is released.
By repeating the storage and release of the magnetic energy as described above, electric power is supplied from the output capacitor
7
to the load
8
. In a stable operation state wherein the storage and release of the magnetic energy of the inductor
4
are balanced with each other, the sum of the integrals of the voltages with respect to time is zero, whereby Equation (1) is established.
Ei
·&dgr;
2
·
T
+(
Ei−Eo
)(&dgr;
1
−&dgr;
2
)
T=Eo
(
1
−&dgr;
1
)
T
  (1)
By arranging Equation (1), Equation (2) is obtained.
E
⁢
 
⁢
o
=
δ1
1
-
δ2
·
E
⁢
 
⁢
i
(
2
)
Equation (2) represents a conversion characteristic. When &dgr;
2
=0, Equation (2) renders Equation (3), whereby the converter operates as a voltage step-down converter.
Eo
=&dgr;
1
·
Ei
  (3)
When &dgr;
1
=1, Equation (2) becomes Equation (4), whereby the converter operates as a voltage step-up converter.
E
⁢
 
⁢
o
=
1
1
-
δ2
·
E
⁢
 
⁢
i
(
4
)
By controlling the duty ratios of the switches
2
and
5
, the value of &dgr;
1
/(
1
−&dgr;
2
) in Equation (2) can be set at any given value in the range of from zero (0) to infinity. Hence, this DC-to-DC converter serves theoretically as a voltage step-up and step-down converter capable of obtaining a desired DC output voltage Eo from the DC input voltage Ei having any given value. For example, U.S. Pat. No. 4,395,675 discloses a DC-to-DC converter controlling the duty ratios of two switches.
FIG. 15
shows a circuit example of a conventionally well-known DC-to-DC converter including a control section
9
for controlling the duty ratios of the switches
2
and
5
.
FIG. 16
a
to
FIG. 16
c
are waveform diagrams showing the waveforms of signals at various parts thereof.
In
FIG. 15
, an error amplification circuit
20
in the control section
9
includes a reference voltage source
200
and resistors
201
and
202
which are connected in series for detecting the DC output voltage Eo. The error amplification circuit
20
includes also an error amplifier
203
whereto are inputted the reference voltage Er of the reference voltage source
200
and a detection voltage Ed obtained by voltage division of the DC output voltage Eo by using the resistors
201
and
202
. A phase compensating capacitor
204
is connected across the input and output terminals of the error amplifier
203
, and an error voltage Ve is output from the output terminal. An oscillation circuit
11
outputs a sawtooth voltage Vt which increases and decreases alternately between two values at a predetermined period. The period of the sawtooth voltage Vt is represented by T and the amplitude thereof is represented by &Dgr;Vt. The level of the voltage rises linearly and drops sharply. A pulse-width control circuit
12
includes an adder
120
for adding a predetermined offset voltage Vos to the error voltage Ve, a first comparator
121
for comparing the output voltage (Ve+Vos) of the adder
120
with the sawtooth voltage Vt, and a second comparator
122
for comparing the error voltage Ve with the sawtooth voltage Vt. The output of the comparator
121
is a first drive signal Vd
1
for turning ON and turning OFF the first switch
2
; the output of the comparator
122
is a second drive signal Vd
2
for turning ON and turning OFF the second switch
5
.
The waveform diagram of
FIG. 16
a
shows the sawtooth voltage Vt, the error voltage Ve and the output voltage (Ve+Vos) of the adder
120
.
FIG. 16
b
and
FIG. 16
c
show the first drive signal Vd
1
and the second drive signal Vd
2
, respectively. In a left end portion A of the waveform diagram of
FIG. 16
a
, the sawtooth voltage Vt is higher than the error voltage Ve, and the waveform of the sawtooth voltage Vt intersects the waveform of the output voltage (Ve+Vos). In a central portion B, the waveform of the sawtooth voltage Vt intersects the waveform of the error voltage Ve and the waveform of the output voltage (Ve+Vos). In a right end portion C, the sawtooth voltage Vt is lower than the output voltage (Ve+Vos).
The operat

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