DC offset reduction in a transmitter

Details DC offset reduction in a transmitter DC offset reduction in a transmitter

1996-10-23

1998-08-11

Vo, Don N.

Pulse or digital communications

Transmitters

Antinoise or distortion

455115, 455126, 330107, H03C 308

Patent

active

057938172

ABSTRACT:
A transmitter comprising at least first and second phase related signal paths, respective frequency up-converters, a combiner for combining the output of the respective frequency up-converters and for supplying the combined signal to a power amplifier. A feedback loop is provided which has a coupler for deriving a portion of the power amplifier output signal and supplying it to first and second phase related feedback paths. Each of the feedback paths comprises frequency down-converters. The dc offset is measured at the respective inputs of the frequency up-converters when the feedback around the linearization loop is reduced to zero without altering the dc offsets produced at the outputs of the frequency down-converters. Subtractors subtract the measured dc offsets from the feedback loop error signals.

REFERENCES:
patent: 5012208 (1991-04-01), Makinen et al.
patent: 5396196 (1995-03-01), Blodgett
patent: 5574994 (1996-11-01), Huang et al.
patent: 5584059 (1996-12-01), Turney et al.
patent: 5623226 (1997-04-01), Whitmarsh et al.

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