DC-offset eliminating method and receiving circuit

Details DC-offset eliminating method and receiving circuit DC-offset eliminating method and receiving circuit

2006-05-23

2006-05-23

Nguyen, Chau (Department: 2661)

Multiplex communications

Generalized orthogonal or special mathematical techniques

Quadrature carriers

C370S206000, C370S516000, C375S148000, C375S150000

Reexamination Certificate

active

07050389

ABSTRACT:
A DC-offset eliminating circuit changes a coefficient α for determining a DC-offset follow-up speed. The coefficient α is changed to a smaller value or 0 in a case where a signal showing a detection that a reception is ceased, is received from a signal-end detecting circuit, or in a case where a signal for partly turning off the circuits for the reduction of power consumption is received from a control circuit, if the received frame is not destined for the receiver itself. The circuit remains the coefficient α to a smaller value immediately after the reception is resumed. Additionally, the circuit returns the coefficient α to the normal value in response to the reception of a signal showing that an alignment signal is detected immediately after a preamble portion. The circuit then reduces the DC-offset follow-up speed as much as possible at the time when the preamble portion is received, thereby avoiding the DC-offset deviation caused by the preamble patterns.

REFERENCES:
patent: 5459679 (1995-10-01), Ziperovich
patent: 5475714 (1995-12-01), Turner
patent: 5629960 (1997-05-01), Dutkiewicz et al.
patent: 5886842 (1999-03-01), Ziperovich
patent: 6400778 (2002-06-01), Matui
patent: 6504884 (2003-01-01), Zvonar

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