DC offset correction adaptable to multiple requirements

Details DC offset correction adaptable to multiple requirements DC offset correction adaptable to multiple requirements

2000-02-29

2001-11-13

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Converter compensation

C455S234200

Reexamination Certificate

active

06317064

ABSTRACT:

CROSS REFERENCE TO RELATED DOCUMENTS
This application is related to patent application Ser. No. 09/515,286 by Tilley, et al., entitled “Method and Apparatus for Settling and Maintaining a DC Offset,” which is a continuation-in-part application Ser. No. 09/290,564 filed Apr. 13, 1999, Tilley, et al., entitled “Method and Apparatus for Settling a DC Offset,” and also related to patent applications Ser. No. 09/575,271 Charles R. Ruelke, entitled “DC Offset Correction Loop for Radio Receiver,” and Ser. No. 09/515,843 by Tilley, et al., entitled “Enhanced DC Offset Correction Through Bandwidth and Clock Speed Selection,” filed concurrently herewith, assigned to Motorola, Inc., and incorporated herein by reference.
TECHNICAL FIELD
This invention relates to techniques and apparatus for carrying out correction of DC offsets in electronic circuits. This invention is especially suitable for situations where multiple, possibly conflicting, requirements for offset correction are needed.
BACKGROUND OF THE INVENTION
Radio receivers, including direct conversion receivers and Zero IF (ZIF) receivers, as well as other types of electronic devices (e.g. radio transmitters) often require that a DC offset be corrected in order to permit proper operation of the device. When a DC offset is present, it can be amplified by direct coupled amplifiers, thereby distorting the signal being processed or even saturating the amplifiers' output at their supply limits, thus rendering the device inoperable. Therefore, DC offsets normally have to be corrected or compensated in some manner.
The requirements for such compensation vary depending upon the pplication. For example, in certain applications for DC offset correction, there is a requirement that the speed of settling the offset correction loop be very fast. For example, in GSM radio receivers, the DC offset correction circuit must be settled to within ±30 mV maximum total error within 400 &mgr;S at the output of the baseband filter. This is a very stringent requirement to be met. Once the circuit is settled, even small changes in DC offset can present problems such as saturation of the baseband signal path. Fortunately, in this environment there are times where it is guaranteed that no signal is present. This time can be advantageously utilized for correction of the offset.
For other systems, however, there may be no time where it can be guaranteed that a signal will not be present. For these systems, a different type of DC offset correction might be required.
For GSM and other Time Division Multiple Access (TDMA) formats, the requirements vary substantially. Moreover, the requirements are different for various forms of continuous transmission radio devices (e.g. traditional two-way radio devices which are not TDMA devices). With the advent of multiple format communication devices (e.g. the iDEN™ telephone transceiver produced by Motorola, Inc.), there is a need for a versatile form of DC offset correction which can be configured to a variety of requirements with the same basic circuit configuration.


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