DC offset cancellation techniques

Amplifiers – Signal feedback – Amplifier in signal feedback path

Reexamination Certificate

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Details

C330S009000

Reexamination Certificate

active

06819172

ABSTRACT:

FIELD
The subject matter disclosed herein generally relates to DC offset cancellation devices.
DESCRIPTION OF RELATED ART
FIG. 1
depicts a conventional wide band amplifier that includes a DC offset cancellation circuit
100
and voltage amplifier
105
. DC offset cancellation circuit
100
may include transconductive amplifier
102
-B and input termination resistors
110
. Voltage amplifier
105
may include a transconductive amplifier
102
-A and loads
120
.
Input return loss measures how much power loss occurs for an increment of incident power. An input return loss value is defined mathematically as −20*log
10
(S
11
), where S
11
represents a ratio of (a) power reflected from input terminals to (b) power incident to such input terminals. The DC offset cancellation circuit
100
of
FIG. 1
may have an S
11
value represented by the following relationship:
(Z
in
−R)/(Z
in
+R), where
Z
in
is the input impedance of the DC offset cancellation circuit
100
(as measured from terminal INPUT), and
R is the resistance of a single ended resistor
110
measured with respect to AC ground.
The input impedance, Z
in
, may be equivalent to a single resistor
110
in parallel with an input capacitance of amplifier
102
-A and in parallel output capacitance of amplifier
102
-B. As the frequency of an input signal to terminal INPUT increases, the input impedance, Z
in
, decreases. Consequently, input return loss may increase with increasing frequency. Therefore, DC offset cancellation circuit
100
may have an undesirable impact on input return loss performance for high frequency input signals.


REFERENCES:
patent: 4227155 (1980-10-01), Lerma
patent: 4374362 (1983-02-01), Sutherland et al.
patent: 5059918 (1991-10-01), Brahms et al.
patent: 6429697 (2002-08-01), Amazeen et al.

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