DC offset cancellation

Details DC offset cancellation DC offset cancellation

2002-09-16

2003-11-04

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S358000

Reexamination Certificate

active

06642767

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to DC offset cancellation. More specifically, DC offset cancellation in a direct conversion transceiver is disclosed.
BACKGROUND OF THE INVENTION
In general, when using a direct conversion structure in an RF transceiver unit, the error rate increases during demodulation, due to the DC offset generated after the frequency conversion. There have been attempts to compensate the DC offset to ameliorate the noise problem.
FIG. 1
is a diagram illustrating an existing DC offset compensation technique. This technique passes the signal containing DC offset through a High Pass Filter HPF to eliminate the DC component. Its advantage is that the circuit can be very simple.
However, the signal is corrupted when it contains a DC component. Also, the data rate of the corner frequency must be 0.1% or less for the signal decay to be ignored. Additionally, if the corner frequency of the HPF is low, data may be lost temporarily during initialization.
FIG. 2
is a block diagram illustrating a feed-forward DC offset compensation technique. A baseband signal that passes through mixer
21
is converted into a digital signal by Analog to Digital Converter ADC
22
. The offset is processed in a Digital Signal Processor DSP
23
. The signal is then converted into an analog signal in Digital to Analog Converter DAC
24
. The DC offset is then cancelled in the Level Shifter installed on the path of Mixer
21
on the basis of the converted analog signal.
FIG. 3
is a block diagram illustrating a feedback DC offset compensation technique. A baseband signal that passes through mixer
31
is converted into a digital signal in ADC
32
, and the offset is processed in DSP
33
. The signal is then converted into an analog signal in DAC
34
. The DC offset is then cancelled in the Level Shifter installed on the path of Mixer
31
on the basis of the converted analog signal.
One disadvantage of the techniques illustrated in
FIGS. 2 and 3
is that each compensation structure takes up a large area on the chip.
FIG. 4
is a diagram illustrating an existing DC offset compensation technique that cancels DC offset in a QPSK direct conversion transceiver. An average value of digital signals is obtained and saved in the memory. The value is then converted to analog, and from which the DC offset is subtracted. This method also has the disadvantage that the circuitry increases the chip size.
FIG. 5
is a diagram illustrating an existing DC offset compensation technique that uses an analog feedback. The DC offset compensator includes two PMOS transistors
51
a
and
51
b
, where the gates of the transistors are connected to each other and the sources are connected to two output terminals out and out_b of mixer
50
. A DC Level Fixing Element also known as Common Mode Feedback Element
52
adjusts the voltage applied to the common gate of transistors
51
a
and
51
b
, as well as fixes the DC level of output signals mixer_out and mixer_out_b according to the feedback input value of the two output signals mixer_out and mixer_out_b coming out from output terminals out and out_b of mixer
50
. DC Level Detectors
53
a
and
53
b
detect the fixed DC level of each of the output signals and obtain the difference from the predefined reference level. Level Shifters
54
a
and
54
b
are installed on the front of the DC level detector along the paths of each output signal and adjust the DC level of each of the output signals according to each of the level differences obtained in the above.
However, the example shown in
FIG. 4
corrects DC offset of signal mixer_out on path
1
through level detector
53
a
and level shifter
54
a
on the basis of an absolute value of the reference level, and corrects DC offset of signal mixer_out_b on path
2
through the level detector
53
b
and level shifter
54
b
on the basis of the reference level. Since the DC offsets of the signals on the two paths are corrected on the basis of an absolute value, it is very probable that a mismatch may occur between the two resultant values after correction. Also, as the level shifters
54
a
,
54
b
are directly connected to the paths of the output signals, the linearity of the signals is decreased, causing distortions.
It would be useful if a DC offset compensation technique could be developed that avoids the difficulties associated with existing DC offset compensation techniques as described above.


REFERENCES:
patent: 6429733 (2002-08-01), Pagliolo et al.
patent: 6483380 (2002-11-01), Molnar et al.
patent: 6509777 (2003-01-01), Razavi et al.
patent: 6535725 (2003-03-01), Hatcher et al.

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