DC offset canceling circuit applied in a variable gain...

Details DC offset canceling circuit applied in a variable gain... DC offset canceling circuit applied in a variable gain...

2002-12-24

2004-06-15

Choe, Henry (Department: 2817)

Amplifiers

With periodic switching input-output

C330S069000, C327S124000

Reexamination Certificate

active

06750703

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DC offset canceling circuit applied in a variable gain amplifier, and particularly to a DC offset canceling circuit which utilizes a chopper stabilization method to cancel DC offset of output stage.
2. Description of the Related Art
Variable gain amplifiers (VGA), which amplify input signal to necessary voltage levels in a system in demodulation process, are widely used in home network transceivers which transmit signals via cable. When the variable gain amplifier is used, a differential input end of an internal operational amplifier has the problem of intrinsic offset, and the intrinsic offset is always in the range of several mV to tens of mV. For wireless or wired communication, the maximum gain of variable gain amplification is up to tens of dE; therefore, the intrinsic offset after amplification will affect the recovery ability of the received signal, the characteristics of parameters of a dynamic range, and signal-to-noise ratio.
A DC offset canceling circuit is shown in
FIG. 1
, disclosed by Yao et al., in “DC offset canceling circuit applied in a variable gain amplifier” U.S. Pat. No. 6,407,630 B1. In
FIG. 1
, a DC offset circuit
26
applied in a variable gain amplifier
25
. The variable gain amplifier
25
includes a first amplifier
21
, a second amplifier
22
, a plurality of switches
201
~
208
, and a plurality of resistors. The DC offset canceling circuit
26
includes a transconductance amplifier
23
and at least one internal capacitor
24
. The switches
201
~
204
adjust the variable gain of the first amplifier
21
. For example, if the switch
201
is closed, the gain is raised; and if the switch
202
is closed, the gain is reduced. The switches
205
~
208
adjust the variable gain of the first amplifier
22
. For example, if the switch
205
is closed, the gain is raised; and if the switch
207
is closed, the gain is reduced. The transconductance amplifier
23
is used to transform the output voltage of the second amplifier
22
to an output current based on a ratio.
The output of the transconductance amplifier
23
is coupled to at least one internal capacitor
24
, and is then fed back to the input of the first amplifier
21
to cancel the DC offset-of the variable gain amplifier
25
. The transconductance amplifier
23
cooperates with the internal capacitor
24
, only about 10 pF or even under 10 pF, as a Gm-C filter. Since the capacitance of the internal capacitor
24
is small, the internal capacitor
24
can be manufactured easily inside an IC, and does not occupy I/O pin.
The DC offset of the first amplifier
21
and the second amplifier
22
is canceled by the transconductance amplifier
23
and capacitor
24
, the Gm-C filter, but the DC offset of the transconductance amplifier
23
is not. There is a need for a novel canceling circuit to cancel the DC offset of the final stage.
According to the prior art, an extremely large chip area is required for implementing the transconductance amplifier so as to reduce the DC offset. However, the DC offset can be reduced by a chopper to saving the chip area according to the present invention described as follows.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a DC offset canceling circuit of a variable gain amplifier.
To achieve the above objects, the present invention provides a DC offset canceling circuit including a transconductance amplifier, at least one internal capacitor, and chopper circuits.
A first chopper circuit
30
is inserted between the output of the variable gain amplifier and the input of the transconductance amplifier. A second chopper circuit is inserted between the output of the transconductance amplifier and the capacitor. The first chopper circuit and the second chopper circuit are controlled by a non-overlap clock signal having a chopping frequency. The first chopper circuit can be merged into the input of transconductance amplifier. The second chopper circuit can be merged into the output of transconductance amplifier.
The DC offset and low frequency noise of the transconductance amplifier, the undesired signal, is translated up to the chopping frequency. The spectrum of the undesired signal is folded back around the chopping frequency. The chopping frequency is much higher than the desired signal bandwidth, thus the size of the undesired signal in the passband of the signal is greatly reduced.
Being chopper-stabilized, the transconductance amplifier and capacitor serve the same function, canceling the DC offset of the variable gain amplifier. The chopper circuit cancels the DC offset of the transconductance amplifier.


REFERENCES:
patent: 5206602 (1993-04-01), Baumgartner et al.
patent: 5293169 (1994-03-01), Baumgartner et al.
patent: 6262626 (2001-07-01), Bakker et al.
patent: 6407630 (2002-06-01), Yao et al.

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