Amplifiers – With amplifier condition indicating or testing means
Reexamination Certificate
2000-07-24
2001-11-13
Pascal, Robert (Department: 2817)
Amplifiers
With amplifier condition indicating or testing means
C330S009000, C330S251000, C330S20700P, C327S307000, C327S124000
Reexamination Certificate
active
06316992
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the operation of digital switching amplifiers. More specifically, the present invention provides methods and apparatus for calibrating a digital switching amplifier to reduce its DC offset voltage.
FIG. 1
is a simplified schematic of a digital switching amplifier
100
which will be used to illustrate the DC offset voltage problem addressed by the present invention. For purposes of illustration, amplifier
100
will be described as operating in the audio frequency range (i.e., 10 Hz to 20 kHz). However, it will be understood that the problem and the solutions described herein apply to a much wider variety of amplifier configurations and operating frequency ranges.
An input audio signal is received by amplifier
100
and converted to a one-bit signal by a noise-shaping oversampled feedback loop which includes loop filter
102
, comparator
104
, break-before-make generator
106
, power stage driver
108
, and power stage
110
. For purposes of this example, loop filter
102
is implemented using a plurality of operational amplifiers configured differentially. The one-bit signal drives the power stage
110
which, in turn, drives a low pass filter comprising inductor
112
and capacitor
114
which recovers the audio signal with which speaker
116
is driven.
Any DC offset inherent in amplifier
100
is amplified by the gain in power stage
110
and appears across speaker
116
. This presents a couple of problems. First, a DC offset voltage across the relatively low impedance (e.g., 4 ohms) of a typical speaker causes a DC current through the speaker which can cause damage to the speaker. Second, such a DC offset voltage could potentially cause a power supply pumping problem which pushes the power supply voltage to a level which could damage both the speaker and the amplifier.
The DC offset in an amplifier configured like amplifier
100
of
FIG. 1
comes from two main sources; the offset in the operational amplifiers of loop filter
102
, and resistor mismatches. Cancellation of offset in operational amplifiers may be accomplished using techniques such as the chopper stabilization technique or the correlated double sampling technique. However, these techniques do not address the offset due to the resistor mismatches. Laser trimming of resistors may be used to eliminate such mismatches, but this approach requires special processing technology and can be prohibitively expensive.
One approach to reducing the DC offset voltage in amplifier
100
is described with reference to the schematic diagram of FIG.
2
. This technique takes advantage of the fact that, in a digital switching amplifier, all of the different offset voltage sources may be modeled by a single input DC offset voltage, cancellation of which effectively cancels the offset contributions of each of the various sources. According to the technique illustrated in
FIG. 2
, a potentiometer
202
is used with amplifier
100
to generate a DC voltage which cancels the amplifier's output offset voltage. Additionally, a decoupling capacitor
204
is used to decouple high frequency noise at this node. This technique has significant drawbacks.
That is, where amplifier
100
is an integrated circuit, components (
202
and
204
) which are external to the integrated circuit amplifier are required. In addition, any variation in the DC offset voltage due to output power level variation and changes in temperature and other environmental conditions requires readjustment of potentiometer
202
. These are both undesirable in most contexts in which such an amplifier is employed.
Another approach to dealing with the DC offset voltage problem is illustrated by the schematic diagram of FIG.
3
. According to this approach, an active integrator circuit
302
provides a feedback path from the output to the input of amplifier
100
. Any DC offset voltage is integrated by integrator
302
thereby generating a DC voltage which is fed back to the amplifier's input stage to cancel the input referred DC offset. Despite the relative simplicity and effectiveness of this approach, there are significant barriers to its practical implementation. First, this technique does not cancel any offset contribution from operational amplifier
304
on which integrator
302
is based. Thus, any DC offset associated with operational amplifier
304
eventually shows up at the output of amplifier
100
.
Second, for specific implementations, the components used to implement integrator
302
may need to be fairly large. For example, in an audio application, the transfer function for the feedback path through integrator
302
must have a very low corner frequency, i.e., below 10 Hz, to avoid having an appreciable effect on the audio signal. Such a low comer frequency requires very large resistor and capacitor values which makes integration with amplifier
100
all but impossible. Therefore, an external circuit would typically need to be used which, as described above, is an undesirable solution.
Therefore, it is desirable that more effective techniques be developed for dealing with DC offset voltages in digital switching amplifiers.
SUMMARY OF THE INVENTION
According to the present invention, a DC offset voltage calibration technique for a digital switching amplifier is provided which generates a DC voltage with reference to the output power level of the amplifier and injects the DC voltage at the amplifier's input to thereby cancel at least a portion of the amplifier's DC offset voltage. In a calibration mode, the DC offset voltage of the amplifier is digitized and these offset data are stored for a number of different output power levels. In operation, information regarding the output power level of the amplifier is used to retrieve the stored information for the indicated output power level and a digital-to-analog converter generates the appropriate voltage to inject at the amplifier's input.
According to a specific embodiment of the invention, portions of the digital switching amplifier are used to effect amplification of the amplifier's offset voltage. That is, because the DC offset voltage range for such an amplifier is typically fairly small (e.g., 50 mV) and the resolution necessary for digitizing the offset voltage fairly high (e.g., less than 50 uV), the DC offset voltage is amplified by the amplifier's loop filter during the calibration process to achieve the necessary resolution.
Thus, the present invention provides an offset voltage calibration circuit for use with a digital switching amplifier. The calibration circuit includes an analog-to-digital converter for converting at least one DC offset voltage associated with the digital switching amplifier to digital offset data. A memory stores the digital offset data. Control circuitry controls the analog-to-digital converter. A digital-to-analog converter coupled to the memory receives the digital offset data and generates an offset compensation voltage for applying to an input port of the digital switching amplifier which thereby cancels at least a portion of the at least one DC offset voltage.
According to a more specific embodiment, an offset voltage calibration circuit for use with a digital switching amplifier is provided. The digital switching amplifier includes an output level control circuit. An analog-to-digital converter converts each of a plurality of DC offset voltages associated with the digital switching amplifier to digital offset data. Each of the DC offset voltages corresponds to a particular output level of the digital switching amplifier as controlled by the output level control circuit. A memory which is configured to receive output level data from the output level control circuit stores the digital offset data. Control circuitry controls the analog-to-digital converter and the memory to effect storage of the digital offset data. A digital-to-analog converter is coupled to the memory. In operation, the memory transmits a portion of the digital offset data to the digital-to-analog converter in
Delano Cary L.
Miao Guoqing
Beyer Weaver & Thomas LLP
Nguyen Patricia T.
Pascal Robert
Tripath Technology Inc.
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