DC insensitive clock generator for optical PRML read channel

Details DC insensitive clock generator for optical PRML read channel DC insensitive clock generator for optical PRML read channel

1999-06-29

2001-04-10

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S118000, C341S120000, C341S139000, C369S047360, C369S059160

Reexamination Certificate

active

06215433

ABSTRACT:

BACKGROUND OF THE INVENTION
A DVD player plays back information stored on a DVD. DVD, an acronym for Digital Video Disc or Digital Versatile Disc, is a relatively new type of Compact-Disc Read-Only-Memory (CD-ROM). With a minimum capacity of approximately 4.7 gigabytes, a DVD can store a full length movie. A DVD player includes an Optical Pick-up Unit (OPU), a Read channel, and a digital video decoder. The OPU converts information read from the DVD into an analog RF signal. The Read Channel takes this RF signal and generates a digital data signal and a synchronous clock signal. The Read Channel couples these signals to a digital video decoder, which decodes the data and converts it into a video format compatible with a TV.
Previously, DVD Read Channels were implemented with analog technology. Analog implementation allows a Read Channel to remove the large DC component that typically forms part of the RF input signal from the OPU with relative ease and minor effect upon the data and clock signals. Unchecked, the low frequency disturbance of the RF input signal can cause the amplitude of the output signal to exceed the expected peak-to-peak amplitude, which can negatively impact the performance of the digital video decoder. Additionally, the baseline wandering resulting from low frequency disturbances of the RF input signal can cause so much clock jitter that the Read Channel phase lock loop (PLL) used to generate the clock may lose lock.
Various considerations now push toward a digital implementation of DVD Read Channels and, in particular, toward Partial Response Maximum Likelihood (PRML) Read Channels. Digital implementation requires a new approach to removing the low frequency disturbances of the RF input signal to the RF channel so that clock jitter does not cause the PLL to lose lock and so that the amplitude of the data signal conforms to a target spectrum.
SUMMARY OF THE INVENTION
The present invention is a clock generator for a Partial Response Maximum Likelihood (PRML) read channel, which produces a clock signal with minimal jitter from an input signal subject to baseline wandering. The clock generator of the present invention includes a Voltage Gain Amplifier (VGA), a low pass filter, an Analog-to-Digital Converter (ADC), a Baseline Wander Correction Circuit, a timing offset detector and loop filter circuit, a Digital-to-Analog Converter (DAC) and a Voltage Controlled Oscillator (VCO). The VGA amplifier amplifies the input signal to produce a first analog signal. The low-pass filter filters the first analog signal to produce a second analog signal. The ADC converts the second analog signal into a first digital signal, operating synchronously with the clock signal. The Baseline Wander Correction Circuitry reduces jitter in the clock signal caused by baseline wandering of the input signal. The Baseline Wander Correction Circuitry produces a second digital signal from the first digital signal, operating synchronously with the clock signal. The second digital signal experiences substantially less baseline wandering than the first digital signal. The timing offset detector and loop filter circuit generates from the second digital signal a timing adjust signal representative of an adjustment to the clock signal. The timing offset detector also operates synchronously with the clock signal. The DAC converts the timing adjust signal into a third analog signal, operating synchronously with the clock signal. The VCO generates the clock signal in response to the third analog signal.


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