DC-free line code and bit and frame synchronization for arbitrar

Cryptography – Communication system using cryptography – Data stream/substitution enciphering

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361246, 371 55, 375287, H04L 2549

Patent

active

054386217

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

This invention pertains generally to the transmission of data and more particularly to a method of encoding digital data to provide a balanced serial data stream that includes bit and frame synchronization control.
Digital data must often be transmitted from one location to another over a communication link. There is a continuing need for systems that can transmit large quantities of data rapidly from point to point, and this has led to the development of very high-speed communication links such as optical fibers and their associated electro-optical components.
It is preferable that a stream of data be encoded for transmission in such a manner that the data stream is balanced. "Balanced" means that over time the stream includes an equal number of logical one bits and logical zero bits. In electrical signal terms, a balanced data stream does not have a DC component whereas an unbalanced stream has a DC component.
Balanced data permits the use of AC-coupled circuits in the communication link. Many communication links do not perform satisfactorily--in fact, some do not perform at all--unless AC-coupled circuits can be used. For example, it may be necessary to use a transformer (an AC coupling device) to prevent ground loops and to reduce common mode signals.
In addition, a laser element in a high-speed fiber optic transmitter requires a regulated drive current. If the laser carries balanced data, the average drive current is independent of the data and therefore is easier to regulate than would be the case if unbalanced data were transmitted. Also, it is easier to separate balanced data from DC bias currents in an optical receiver. Accordingly there has been a need for a method of encoding digital data so that the resulting data stream is balanced before providing the data to a transmitter in a communication link.
A receiver in a digital communication link must be synchronized with an incoming digital signal so that it can extract frame and bit timing information from the signal. This timing information is then used to recover the actual data. Therefore, in addition to the requirement that the data stream be balanced, there is a requirement that the data be encoded in such a way that the receiver can be synchronized with the incoming signal. Such synchronization may be accomplished, for example, by means of a phase-lock loop ("PLL") circuit such as that described in the aforementioned U.S. Pat. No. 4,926,447.
It is also desirable to communicate various control signals to the receiver. These signals may convey additional information or they may be used to regulate the operation of the receiver itself.
A method of providing a balanced data stream is described in Carter, R. O., "Low-Disparity Binary Coding System," Electronic Letters, May 1965, Vol. 1, No. 3, pp 67-68. Briefly, groups of bits are inverted as needed to maintain a balance between the average number of logical one bits and logical zero bits carried by the communication link. An indicator bit is appended to each group to indicate whether that group is being transmitted in inverted form.
An improved version of this method, and apparatus for implementing it, are described in the aforementioned U.S. Pat. No. 5,022,051. This patent also discloses appending a small plurality of M bits to each data word. These appended bits may be used, for example, to indicate whether the data bits have been inverted and they may carry a "master transition" which always occurs in the same relative position in each word for use by the receiver in establishing synchronization with the incoming data stream.
A transition is defined by a change in the logic levels of two adjacent bits. The polarity of a transition is either positive-going, as in a change from a logical zero to a logical one, or negative-going.
Typically, it has been required that a master transition always have the same polarity. Two bits are required to define a master transition that always has the same polarity. The information content of a data stream could be increased by pro

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Walker et al., "A Chipset for Gigabit Rate Data Communication", IEEE Proceedings of the 1989 Bipolar Circuits and Technology Meeting, Sep. 1989, pp. 288-290.

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