Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-10-15
2004-02-03
Berhane, Adolf D. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06686729
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a DC/DC switching regulator and more specifically to a DC/DC switching regulator for low power applications, such as a cellular telephone.
DC/DC switching regulators are part of many power management systems because of the improved power conversion efficiency provided by these regulators over that of linear regulators or low-dropout linear regulators (LDO). Switching regulator designs can achieve efficiency as high as 80-90% compared with efficiencies 25-50% for a LDO. In modem power management systems, switching regulators are often utilized to perform the task of pre-regulating the power supply used by the LDO to produce an overall system efficiency of about 75%.
FIG. 1A
shows a typical prior art buck (voltage reducing) DC/DC switching regulator.
FIG. 1B
shows a typical prior art voltage boost switching regulator. Both circuits have the same essential components including a feedback and control circuit
104
,
154
; a driver
106
,
156
; a switching transistor
108
,
158
; an inductor
112
,
162
; an output capacitor
116
,
166
; a rectifier
114
,
164
, such as a Schottky diode; and a feedback loop
118
,
168
. Circuits that perform both boost and buck are also known in the art (not shown). The operation of these circuits is well known in the art and need not be described in detail here. One of the components of the total power loss of the switching regulator is the power switch gate drive loss. Each of the switching transistors
108
,
158
have an associated parasitic capacitance
110
,
160
which is charged up from the power supply or boosted supply and discharged to ground. All of the power used to charge the gate of the MOSFET is lost when the parasitic capacitance is discharged to ground. The power loss can be expressed as Psw=Cg*Vin*fs where Cg is the parasitic gate capacitance, Vin is the input voltage swing, of the switching transistor and fs is the switching frequency. The power switch, which can be internal or external to the integrated circuit, is typically very large having a width/length exceeding 50k &mgr;m having an associated parasitic gate capacitance in excess of 100 pF. Thus, the switching losses can be a significant portion of the overall losses in the switching regulator, especially at light loads.
In DRAM circuits it is common to drive the gate of a pass transistor to substantially above the array voltage supply level (Vdd) in order that the storage elements of the memory be charged to the full array supply voltage. U.S. Pat. Nos. 5,185,721 and 5,216,290 show circuits in which the capacitor utilized to generate the boost voltage is utilized to store the charge on the parasitic capacitor of the gate of the pass transistor when the gate is to be discharged to ground. See also U.S. Pat. Nos. 3,691,537; 4,030,083; 4,070,653; 4,292,677; and 4,430,730.
SUMMARY OF THE INVENTION
It is a general object of the present invention to improve the switching efficiency of a DC/DC switching regulator.
This and other objects are achieved, in accordance with one aspect of the invention by a voltage converter comprising a semiconductor switch coupled to an inductor, a first capacitor and a rectifier, the semiconductor switch having a gate and being driven between ON and OFF states from first and second voltage sources by a control circuit. A circuit for improving switching efficiency of the semiconductor switch includes a second capacitor and a first transmission gate coupled between the second capacitor and the gate of the semiconductor switch. The control circuit is coupled to the first transmission gate and generates a control signal to turn ON the first transmission gate when the first control circuit isolates the semiconductor switch from the first and second voltage sources, turns OFF the first transmission gate before the control circuit drives the semiconductor switch to a second one of the ON and OFF states, turns on the first transmission gate after the first control circuit isolates the semiconductor switch from the first and second voltage sources and turns OFF the first transmission gate before driving the semiconductor switch from the second of the ON and OFF states, to the first of the ON and OFF states. Thus, a portion of charge stored on a parasitic capacitance of the gate of the semiconductor switch is stored in the second capacitor and reused to partially drive the semiconductor switch from the first of the ON and OFF states to the second one of the ON and OFF states.
Another aspect of the invention includes a DC to DC converter for generating a voltage at an output which is lower than a voltage supplied at an input having a PMOS transistor coupled between the voltage supply and the series connection of an inductor and a capacitor, the voltage across the capacitor being the output voltage. A rectifier is connected in parallel to the series connected inductor and capacitor and a control circuit for the PMOS transistor is coupled to a gate thereof and provides a drive signal between substantially the supply voltage and substantially a reference voltage. A transmission gate is coupled between the gate, a second capacitor and the reference voltage and is responsive to a control voltage generated by the control circuit for driving the transmission gate ON after the gate of the PMOS transistor is isolated from the supply voltage and the reference voltage, driving the transmission gate OFF after a predetermined time interval and before the control circuit drives the gate of the PMOS transistor to substantially the supply voltage, the control circuit isolating the gate of the PMOS transistor before driving the transmission gate ON for a predetermined time interval before the drive signal at substantially the reference voltage is applied to the gate of the PMOS transistor.
A further aspect of the invention comprises a method for operating a voltage converter having a semiconductor switch coupled to an inductor, a first capacitor, and a rectifier, the semiconductor switch being driven between ON and OFF states from first and second voltage sources and having parasitic capacitance at a gate thereof. The semiconductor switch is isolated from the first and second voltage sources. Charge is transferred from the parasitic capacitor to a second capacitor coupled thereto. The charge transfer is terminated and the second capacitor isolated from a remainder of the voltage converter. A ON/OFF state of the semiconductor switch is changed by driving the gate to the other of the first and second voltage sources. The semiconductor switch is isolated from the first and second voltage sources . The second capacitor is coupled to the gate to charge the parasitic capacitor and decoupled prior to driving the semiconductor switch to the other of the ON/OFF states.
A still further aspect of the invention includes a cellular telephone having a voltage converter for powering a telephone circuit, the voltage converter comprising a semiconductor switch coupled to an inductor, a first capacitor and a rectifier, the semiconductor switch having a gate and being driven between ON and OFF states from first and second voltage sources by a control circuit. A second capacitor, a first transmission gate coupled between the second capacitor and the gate of the semiconductor switch, wherein the control circuit is coupled to the first transmission gate and generates a control signal to turn ON the first transmission gate when the control circuit isolates the semiconductor switch from the first and second voltage sources, turns OFF the first transmission gate before the control circuit drives the semiconductor switch to a second one of the ON and OFF states, turns on the first transmission gate after the first control circuit isolates the semiconductor switch from the first and second voltage sources and turns OFF the first transmission gate before driving the semiconductor switch from the second of the ON and OFF states to the first of the ON and OFF states. Thus, a portion of the charge stored on a parasitic capacitor of the g
Evans David W.
Kawamura J. Patrick
Krug James L.
Berhane Adolf D.
Brady III W. James
Kempler William B.
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