Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-02-27
2004-05-04
Vu, Bao Q. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S271000, C323S282000
Reexamination Certificate
active
06731099
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a DC—DC converter, and more particularly, to a DC—DC converter in various types of electronic devices.
A DC—DC converter includes a step-down circuit, which generates a DC output voltage that is lower than a power supply voltage, and a step-up circuit, which generates a DC output voltage that is higher than the power supply voltage. The DC—DC converter further includes a control circuit for receiving a switching signal from an external device to switch the operational mode from a step-up operation to a step-down operation or from a step-down operation to a step-up operation. The DC—DC converter must have an external terminal to receive the switching signal. Accordingly, it is difficult to reduce the size of the DC—DC converter.
Referring to
FIG. 1
, a step-down DC—DC converter
100
includes a control circuit
1
, which is formed on a single semiconductor integrated circuit substrate, and a step-down circuit
2
, which includes a plurality of externally connected devices. The control circuit
1
controls the step-down circuit
2
to decrease an input voltage Vin and generate a DC output voltage Vo.
The control circuit
1
includes an error detection amplifier
3
, which has a minus input terminal for receiving an output voltage Vo of the step-down circuit
2
and a plus input terminal for receiving a reference voltage VR
1
. The error detection amplifier
3
amplifies the differential voltage between the output voltage Vo and the reference voltage VR
1
and provides the amplified signal to a first plus input terminal of a PWM comparator
4
.
A duty setting signal DTC, which is a DC voltage, is provided to a second plus input terminal of the first PWM comparator
4
. An oscillation circuit (not shown) provides a triangular wave signal VCT to a minus input terminal of the first PWM comparator
4
.
The first PWM comparator
4
compares the output signal of the error detection amplifier
3
or the duty setting signal DTC, whichever one has the lower voltage, with the triangular wave signal VCT. In each cycle of the triangular wave signal, the first PWM comparator
4
generates a comparison output signal SG
1
at a low level when the voltage of the triangular wave signal VCT is higher than that of the signal having the lower voltage. When the voltage of the triangular wave signal VCT is lower than that of the signal having the lower voltage, the first PWM comparator
4
generates the comparison output signal SG
1
at a high level.
A voltage shift circuit
5
shifts the output signal of the error detection amplifier
3
to a high potential and provides the shifted signal to a plus input terminal of a second PWM comparator
6
. A minus input terminal of the second PWM comparator
6
is provided with the triangular wave signal VCT. The second PWM comparator
6
compares the shifted signal and the triangular wave signal VCT. In each cycle of the triangular wave signal VCT, the second PWM comparator
6
generates a comparison signal SG
2
at a low level when the voltage of the triangular wave signal VCT is higher than that of the shifted signal and generates the comparison signal at a high level when the voltage of the triangular wave signal VCT is lower than that of the shifted signal.
The comparison output signal SG
1
of the first PWM comparator
4
is provided to a switch circuit
8
a
via an inverter circuit
7
a
and to a switch circuit
8
b
. The comparison output signal SG
2
of the second PWM comparator
6
is provided to the switch circuit
8
b
via an inverter circuit
7
b
and to the switch circuit
8
a.
The switch circuits
8
a
,
8
b
are provided with a switching signal CH from an external device (not shown) via a terminal T. When the switching signal CH goes low, the switch circuit
8
a
functions to provide the output signal of the inverter circuit
7
a
to a drive circuit
9
a
, and the switch circuit
8
b
functions to provide the output signal of the inverter circuit
7
b
to a drive circuit
9
b.
The drive circuit
9
a
is operated by the power provided from a power supply VCC and the ground GND. The drive circuit
9
b
is operated by the power provided from a power supply VDD and the ground GND. Although the voltage of the power supply VCC is higher than that of the power supply VDD, the two voltages may be the same.
The drive circuit
9
a
provides its drive output signal to the gate of a p-channel MOS transistor Tr
1
in the step-down circuit
2
. The drive circuit
9
b
provides its drive output signal to the gate of an n-channel MOS transistor Tr
2
in the step-up circuit
2
. In response to the drive signals from the control circuit
1
, the transistors Tr
1
, Tr
2
are alternately activated.
The step-down circuit
2
includes the transistors Tr
1
, Tr
2
, a diode D
1
, a coil L
1
, and a capacitor C
1
. The alternate activation of the transistors Tr
1
, Tr
2
in the step-down circuit
2
decreases the input voltage Vin and generates a step-down DC output voltage Vo.
In the step-down DC—DC converter
100
, with reference to
FIG. 3
, the duty setting signal DTC is set at a voltage that is higher than the maximum voltage of the triangular wave signal VCT. When the DC output voltage Vo of the step-down circuit
2
decreases, the duty of high level in the comparison signals SG
1
, SG
2
, which are generated by the first and second PWM comparators
4
,
6
, increases. This lengthens the activated time of the transistor Tr
1
and shortens the activated time of the transistor Tr
2
. As a result, the DC output voltage Vo of the step-down circuit
2
increases.
When the DC output voltage Vo of the step-down circuit
2
increases, the duty of high level in the comparison signals SG
1
, SG
2
, which are generated by the first and second PWM comparators
4
,
6
, decreases. This shortens the activated time of the transistor Tr
1
and lengthens the activated time of the transistor Tr
2
. As a result, the DC output voltage Vo of the step-down circuit
2
decreases.
FIG. 2
is a schematic circuit diagram of a step-up DC—DC converter
200
that includes a step-up circuit
10
. The step-up circuit
10
is driven by the control circuit
1
and increases an input voltage Vin to generate an output voltage Vo.
When the control circuit
1
is provided with the switching circuit CH at a high level, the drive circuit
9
a
is provided with the comparison output signal of the second PWM comparator
6
via the switch circuit
8
a
, and the drive circuit
9
b
is provided with the comparison output signal of the first PWM comparator
4
via the switch circuit
8
b.
The drive circuit
9
a
provides its drive output signal to the gate of a p-channel MOS transistor Tr
3
. The drive circuit
9
b
provides its drive output signal to the gate of an n-channel MOS transistor Tr
4
. In response to the drive signals from the control circuit
1
, the transistors Tr
3
, Tr
4
are alternately activated.
The step-up circuit
10
includes the transistors Tr
3
, Tr
4
, a diode D
2
, a coil L
2
, and a capacitor C
2
. The alternating activation of the transistors Tr
3
, Tr
4
in the step-up circuit
10
increases the input voltage Vin and generates a step-up DC output voltage Vo.
In the step-up DC—DC converter
200
, with reference to
FIG. 4
, the duty setting signal DTC is set at a voltage that is lower than the maximum voltage of the triangular wave signal VCT (more specifically, a voltage corresponding to about 70 percent of the amplitude of the triangular wave signal VCT).
When the DC output voltage Vo of the step-up circuit
10
decreases, the duty of high level in the comparison signals SG
1
, SG
2
, which are generated by the first and second PWM comparators
4
,
6
, increases. This shortens the activated time of the transistor Tr
3
and lengthens the activated time of the transistor Tr
4
. As a result, the DC output voltage Vo of the step-up circuit
10
increases.
When the DC output voltage Vo of the step-up circuit
10
increases, the duty of high level in the comparison signals SG
1
, SG
2
, which are generated by the first
Inatomi Koichi
Nagai Ryuta
Arent & Fox PLLC
Fujitsu Limited
Vu Bao Q.
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