Electricity: power supply or regulation systems – In shunt with source or load – Using choke and switch across source
Reexamination Certificate
2002-07-25
2003-11-04
Vu, Bao Q. (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using choke and switch across source
C323S284000, C323S286000
Reexamination Certificate
active
06642696
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to DC-DC converters and in particular a DC-DC converter that does not require an external resistor connected to the output side for regulation, and thereby improves transformation efficiency and stability of the output voltage.
BACKGROUND OF THE INVENTION
A DC-DC converter can convert a supplied DC voltage to another constant voltage for the load circuit, independent of variation in the load. Usually, a DC-DC converter of this type generates a feedback control voltage in correspondence with the output voltage, and generates a switching control signal in correspondence with said feedback control voltage, with said switching control signal used in controlling the feed of the DC voltage to the load side so as to stabilize the output voltage.
FIG. 8
is a diagram illustrating an example of the constitution of a conventional voltage-mode DC-DC converter. This DC-DC converter is composed of output filter unit
10
, feedback control unit
20
, pulse width modulating unit (PWM modulating unit)
30
, and switching unit
40
.
Switching unit
40
is composed of PMOS transistor M
1
and NMOS transistor M
2
connected in series between input power source voltage V
in
and ground potential GND, as well as diode D
1
. PWM modulation pulse S
p
fed from PWM modulation unit
30
is applied to the gates of transistors M
1
and M
2
, respectively. One end of coil L
e
of output filter unit
10
is connected to node ND
1
, which is the point of connection between the drains of transistors M
1
and M
2
.
In switching unit
40
, transistors M
1
and M
2
are controlled to be ON and OFF alternately in correspondence with PWM modulation pulse S
p
. For example, when PWM modulation pulse S
p
is at low level, transistor M
1
is ON, while transistor M
2
is OFF. Conversely, when PWM modulation pulse S
p
is at high level, transistor M
1
is OFF, and transistor M
2
is ON.
When transistor M
1
is ON, current I
c
is fed from power source voltage V
in
to output filter unit
10
. When transistor M
1
is OFF and transistor M
2
is ON, the output current to the load side is maintained by coil L
e
provided in output filter unit
10
.
Also, diode D
1
is arranged to absorb variation in the switching timing of transistors M
1
and M
2
so as to increase the voltage conversion efficiency.
Output filter unit
10
takes the current fed from switching unit
40
as input, and smoothes said current by means of output capacitor C
out
, and sends output voltage V
out
to the load.
Feedback control unit
20
generates feedback voltage V
c
in correspondence with voltage V
out
output from output filter unit
10
to the load side, and sends said voltage to PWM modulation unit
30
. Feedback control unit
20
is composed of resistance elements R
1
, R
2
, R
3
, capacitor C
1
, and differential amplifier AMP
1
. Resistance elements R
2
and R
3
are connected in series between the output terminal of output voltage V
out
and ground potential GND, and they divide output voltage V
out
to generate divided voltage V
o1
. Capacitor C
1
and resistance element R
1
are connected in series between the inverting input terminal and the output terminal of differential amplifier AMP
1
.
Voltage V
o1
is applied to the inverting input terminal of differential amplifier AMP
1
. Also, a prescribed reference voltage V
ref
is applied to the non-inverting input terminal of differential amplifier AMP
1
.
Differential amplifier AMP
1
and circuit elements connected to it, such as capacitor C
1
and resistance element R
1
connected in series between its inverting input terminal and output terminal, form a comparator and an integrator.
That is, the level of the integration voltage of the voltage divider voltage V
o1
and that of reference voltage V
ref
are compared with each other in feedback control unit
20
, and control voltage (feedback voltage) V
c
is output in correspondence with the result of said comparison. Because reference voltage V
ref
is at a constant level, when divided voltage V
o1
rises, the voltage level of control voltage V
c
falls. Conversely, when divided voltage V
o1
falls, the voltage level of control voltage V
c
rises.
In correspondence with control voltage V
c
from feedback control unit
20
and the sawtooth wave generated by sawtooth generator
32
, PWM modulation unit
30
generates pulse signal S
p
that has its pulse width modulated (PWM modulation pulse), which is sent to switching unit
40
.
As shown in the figure, PWM modulation unit
30
is composed of comparator CMP
1
and sawtooth wave generator
32
. Control voltage V
c
is applied to the inverting input terminal of comparator CMP
1
, and the sawtooth signal generated by sawtooth wave generator
32
is applied to its non-inverting input terminal. If the output ability of comparator CMP
1
is insufficient, or if the signal level is not in agreement with that of switching unit
40
, one may also add an output driver and a level shift circuit to the output of comparator CMP
1
.
Pulse signal S
p
that has its pulse width modulated in correspondence with control voltage V
c
is output from the output terminal of comparator CMP
1
. Here, assuming the offset voltage of the sawtooth wave generated by sawtooth generator
32
to be constant, when the level of control voltage V
c
rises, the pulse width on the positive half of output pulse signal S
p
become smaller, while the pulse width on the negative half becomes larger. Conversely, when the level of control voltage V
c
falls, the pulse width on the positive half of pulse signal S
p
becomes larger, and the pulse width on the negative half becomes smaller.
In the following, we will examine the operation of the feedback control of the DC-DC converter having the aforementioned constitution.
For example, when the level of output voltage V
out
sent to the load falls due to load variation or the like, divided voltage V
o1
also falls, and control voltage V
c
output from feedback control unit
20
rises. As a result, in PWM modulation unit
30
, the pulse width on the positive half of pulse signal S
p
becomes smaller, while the pulse width on the negative half becomes larger.
In switching unit
40
, when pulse signal S
p
is at high level, that is, when pulse signal S
p
is positive, transistor M
1
is OFF, while transistor M
2
is ON. Also, when pulse signal S
p
is at low level, that is, when pulse signal S
p
is negative, transistor M
1
is ON, while transistor M
2
is OFF. Consequently, during the period when pulse signal S
p
is negative, input power source voltage V
in
is applied to coil L
e
of output filter unit
10
. During the period when pulse signal S
p
is positive, a current is fed to the load side by means of coil L
e
of filter unit
10
.
Consequently, as explained above, when voltage V
out
sent from output filter unit
10
falls due to variation in the load or the like, the pulse width on the positive half of modulation pulse signal S
p
output from PWM modulation unit
30
becomes smaller, and the pulse width on the negative half becomes larger. Consequently, in switching unit
40
, the ON time of transistor M
1
is controlled to be longer than the ON time of transistor M
2
during each period of pulse signal S
p
. As a result, control is performed so that the proportion of time when input power source voltage V
in
is applied to output filter unit
10
becomes larger, and output voltage V
out
becomes higher.
On the other hand, when output voltage V
out
rises, its divided voltage V
o1
also rises, and the voltage level of control voltage V
c
output from feedback control unit
20
falls. As a result, in PWM modulation unit
30
, modulation is performed so that the pulse width on the positive half of pulse signal S
p
becomes larger, and the pulse width on the negative half becomes smaller. Consequently, in switching unit
40
, control is performed so that the ON time of transistor M
1
is shorter than the ON time of transistor M
2
. Consequently, control is performed so that the proportion of time when input power source voltage V
in
Brady III W. James
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Vu Bao Q.
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