Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2007-05-29
2007-05-29
Patel, Rajnikant B. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C363S071000
Reexamination Certificate
active
11121067
ABSTRACT:
A control circuit for a DC-DC converter that prevents erroneous operations during high ON-duty operation. In response to an H-level pulse signal, a random delay circuit generates a delayed pulse signal that rises to an H level within one cycle of the pulse signal. The random delay circuit randomly changes the delay time of the delayed pulse signal. Even if noise causes the timing at which a current comparison signal rises to an H level to be delayed to later than the timing at which an H-level pulse signal is provided to the set terminal of an FF circuit, the FF circuit receives at its reset terminal an H-level delayed pulse signal that is provided prior to the H-level pulse signal. The FF circuit then inactivates the output transistor.
REFERENCES:
patent: 6534930 (2003-03-01), Ito et al.
Arent & Fox LLP
Fujitsu Limited
Patel Rajnikant B.
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