DC/DC converter and a controlling circuit thereof

Details DC/DC converter and a controlling circuit thereof DC/DC converter and a controlling circuit thereof

2000-01-25

2001-09-11

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S284000, C323S282000

Reexamination Certificate

active

06288524

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DC/DC converter and a controlling method thereof, and more particularly to a current-mode DC/DC converter.
2. Description of the Related Art
A DC/DC converter is a device for converting a certain DC voltage into a different DC voltage, and is used in various fields.
FIG. 1
is a circuit diagram of a conventional DC/DC converter. This DC/DC converter operates with PWM (Pulse-Width Modulation), and is sometimes called a switching regulator. This DC/DC converter monitors an electric current flowing through an inductor, and adjusts an output DC voltage based on the current.
Switches M
1
and M
2
are, for example, a pair of MOS transistors which are connected in series and are respectively turned on or off according to the driving signals V
U
and V
L
provided from a driving circuit
101
. An input voltage V
in
is applied to the switch M
1
, while the switch M
2
is grounded.
Fundamentally, the switches M
1
and M
2
are alternately turned on or off according to the state of a flip-flop
102
. When the flip-flop
102
is in a set state, the switch M
1
is ON and switch M
2
is OFF, and an inductor current I
L
which flows via an inductor L increases (ramps up). If the flip-flop
102
is in a reset state, the switch M
1
is OFF and switch M
2
is ON, and the inductor current I
L
decreases (ramps down). An output capacitor C
out
is arranged to smooth an output voltage.
In this DC/DC converter, the output voltage V
out
and the inductor current I
L
are used as feedback signals for controlling the switches M
1
and M
2
. An error amplifier
103
amplifies the difference between the output voltage V
out
(or a voltage obtained by dividing the output voltage V
out
with a resistor network composed of resistors R
1
and R
2
) and a predetermined reference voltage V
ref
, and outputs the amplified difference as a current instruction signal I
cont
. A comparator
104
makes a comparison between an inductor current signal I
curr
representing the inductor current I
L
and the current instruction signal I
cont
output from the error amplifier
103
. Then, the comparator
104
outputs the result of the comparison as a reset signal V
res
.
An oscillator
105
generates a set signal. The set signal is a pulse signal which is synchronous with the oscillation frequency of the oscillator
105
. The set signal is input to the set terminal of the flip-flop
102
via an AND gate (one of whose inputs is a negative logic)
106
, while the reset signal from the comparator
104
is input to the reset terminal of the flip-flop
102
.
Next, the operations of the DC/DC converter are explained by referring to FIG.
2
. Upon receipt of the set pulse from the oscillator
105
, the flip-flop
102
enters the set state. When the flip-flop
102
enters the set state, the driving signal V
L
is changed from “H” to “L” and the driving signal V
U
is changed from “L” to “H”. As a result, the switch M
2
is turned off and switch M
1
is turned on. Then, the inductor current I
L
starts to increase.
When the inductor current signal I
curr
representing the inductor current I
L
reaches the current instruction signal I
cont
being the output of the error amplifier
103
, the output of the comparator
104
is changed from “L” to “H”, and is provided to the reset terminal of the flip-flop
102
.
Upon receipt of “H” at the reset terminal, the flip-flop
102
enters the reset state. When the flip-flop
102
enters the reset state, the driving signal V
U
is changed from “H” to “L” and the driving signal V
L
is changed from “L” to “H”. Consequently, the switch M
1
is turned off and the switch M
2
is turned on. Then, the inductor current I
L
starts to decrease. Thereafter, the above described operations are repeated when the next set pulse is generated by the oscillator
105
and the generated set pulse is input to the set terminal of the flip-flop
102
. That is, the DC/DC converter fundamentally repeats the above described operations in synchronization with the oscillation frequency of the oscillator
105
.
As described above, with the DC/DC converter shown in
FIG. 1
, the output voltage V
out
is held constant by controlling the inductor current I
L
with the use of the current instruction signal I
cont
generated based on the output voltage V
out
. The output voltage to be held by this DC/DC converter is determined by the reference voltage V
ref
.
Fundamentally, the switches M
1
and M
2
are alternately turned on and off. However, if these two switches are simultaneously ON, their elements can possibly be destroyed by a large current. Accordingly, what is called a dead time is provided to the driving signals V
u
and V
L
in order to prevent the switches M
1
and M
2
from being simultaneously ON.
Normally, noise occurs in a DC/DC converter when a switch is turned on or off, and frequently causes erroneous operations. A problem caused by the noise at the switching timing is described next by referring to FIG.
3
.
At a time T
1
, the set pulse of the set signal is generated and provided to the set terminal of the flip-flop
102
. Here, the AND gate
106
is assumed to be open at the time T
1
.
When the flip-flop
102
enters the set state according to this set pulse, the inductor current I
L
then starts to increase as described above. When the inductor current signal I
curr
representing the inductor current I
L
reaches the current instruction signal I
cont
, the output of the comparator
104
(reset signal) is changed from “L” to “H”. Because a circuit delay exists, a predetermined amount of time is required from when the inductor current signal I
curr
exceeds the current instruction signal I
cont
until when the reset signal is actually changed from “L” to “H”.
When the reset signal is changed to “H”, the flip-flop
102
enters the reset state and the inductor current I
L
then starts to decrease as described above.
When the next pulse is generated and the flip-flop
102
is changed from the reset state to the set state at a time T
3
, the driving signal V
L
for controlling the switch M
2
is changed from “H” to “L”. As a result, the switch M
2
is turned off. In the meantime, the dead time is arranged for the driving signal V
U
for controlling the switch M
1
. Therefore, the switch M
1
remains OFF.
When the switch M
2
is turned off, noise occurs in the inductor current signal I
curr
. Furthermore, if the inductor current signal I
curr
exceeds the current instruction signal I
cont
due to this noise, the reset signal is changed from “L” to “H”. However, the predetermined amount of time is required from when the inductor current signal I
curr
exceeds the current instruction signal I
cont
until when the reset signal is actually changed from “L” to “H”, as described above. Therefore, the reset signal is changed from “L” to “H” at a time T
5
.
In the meantime, the driving signal V
U
for controlling the switch M
1
is changed from “L” to “H” at the timing (time T
4
) when the dead time elapses from the time T
3
. Accordingly, in this case, the switch M
1
is immediately turned off at the time T
5
after being turned on at the time T
4
. Namely, in this case, the inductor current I
L
continues to decrease after the time T
5
until the next set pulse is generated at a time T
6
.
When the next set pulse is generated at the time T
6
after that, the flip-flop
102
is changed from the reset state to the set state and the inductor current I
L
continues to increase until the inductor current signal I
curr
reaches the current instruction signal I
cont
.
When noise, etc. occurs in the signal for controlling the switch M
1
or M
2
as described above, the inductor current I
L
may sometimes become unstable. That is to say, the inductor current I
L
regularly change in an ideal state where no noise occurs, as shown in FIG.
2
. However, the inductor current I
L
may irregularly change in some cases when noise occurs, as shown in FIG.
3
. Since the time period during which the switch M
1
is ON becomes shorter than that

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