Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2006-07-11
2006-07-11
Sterrett, Jeffrey (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S351000
Reexamination Certificate
active
07075279
ABSTRACT:
A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.
REFERENCES:
patent: 4920246 (1990-04-01), Aoki
patent: 6297623 (2001-10-01), Balakrishnan et al.
patent: 6711035 (2004-03-01), Tomioka
Katoh Tomonari
Manabe Katsuhiko
Matsushima Makoto
Sugiyama Minoru
Ueda Tadayoshi
Dickstein , Shapiro, Morin & Oshinsky, LLP
Sterrett Jeffrey
LandOfFree
DC converter with halt mode setting means does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DC converter with halt mode setting means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DC converter with halt mode setting means will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3538425