Boots – shoes – and leggings
Patent
1990-07-10
1993-01-12
Hecker, Stuart N.
Boots, shoes, and leggings
395775, 36424342, 364DIG1, 364DIG2, G06F 1200, G06F 1340
Patent
active
051796899
ABSTRACT:
A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.
REFERENCES:
patent: 3757306 (1973-09-01), Boone
patent: 4074351 (1978-02-01), Boone et al.
patent: 4096567 (1978-06-01), Millard et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4527237 (1985-07-01), Frieder et al.
patent: 4564900 (1986-01-01), Smitt
patent: 4577282 (1986-03-01), Caudel et al.
patent: 4620275 (1986-10-01), Wallach et al.
patent: 4701844 (1987-10-01), Thompson et al.
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 4896264 (1990-01-01), Boddie
Allen, Jonathan; Computer Architecture for Digital Signal Processing, Proceedings of the IEEE, vol. 73, No. 5, May, 1985, pp. 852-862.
DSP Microprocessor, Analog Devices, ADSP-2100, p. 1009, One Technology Way, P.O. Box 9106, Norwood, MA 02062.
Caren, Craig J. et al.; THAM 13.1: A 60 ns CMOS DSP with On-Chip Instruction Cache, 1987 IEEE International Solid State Circuit Conf., pp. 156-157 and 378-379.
Kogge, Peter M.; The Architecture of Pipelined Computers, McGraw-Hill Book Company, Hemisphere Publishing Corporation, copyright 1981, pp. 39-47.
Roesgen, J. P.; A High Performance Microprocessor for DSP Applications, ICASSP 86, Tokyo, 1986 IEEE, pp. 397-400.
Leach Jerald G.
Simar Jr. L. Ray
Donaldson Richard L.
Grossman Rene E.
Hecker Stuart N.
Holland Robby T.
Texas Instruments Incorporated
LandOfFree
Dataprocessing device with instruction cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dataprocessing device with instruction cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dataprocessing device with instruction cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1226157