Datapath control circuit with adjustable delay elements

Details Datapath control circuit with adjustable delay elements Datapath control circuit with adjustable delay elements

2000-08-02

2003-06-17

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S299000

Reexamination Certificate

active

06580303

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to control circuits, and in particular to asynchronous control circuits having adjustable delay elements.
Control circuits for controlling data flow in datapath circuits are well known for use in asynchronous systems. For example, in a paper entitled “Counterflow Pipeline Processor Architecture,” by R. Sproul, I. Sutherland, and C. Molnar, Sun Microsystems Laboratories, Inc., Publication No. SMLI TR-94-25, April 1994, counterflowing datapaths are controlled using a sequence of Muller C-elements.
FIG. 1
of this application illustrates a simple control system such as described in that paper.
In a pipeline processor such as described in the paper mentioned above, there are at least two uses for the control system. First, the control system can provide for concurrent arbitration and data advance. Second, if there are multiple instruction pipes, the interlocked control system can help keep the instruction streams in the multiple pipes in proper order. That is, instructions in one processor are prevented from passing those in another processor.
FIG. 1
depicts a system in which a first-in first-out (FIFO) datapath is controlled by a network of Muller C-elements. The series of interlinked Muller C-elements receive request and acknowledge signals, and in response control processing cells (PC). Data or instructions, or both, are introduced at the input terminals of the processing cells and propagate along the FIFO processor, eventually emerging at the output terminals in the same order as introduced. Each cell performs a desired operation with the instructions or the data. The Muller C-elements assure that the processor passes information through the FIFO in sequence and that information advances only when it is ready to advance. The Muller C-elements provide a sequential activation of the processing cells, resulting in processing of the information through the datapath.
Each Muller C-element shown in
FIG. 1
functions to produce an output event after each of its input terminals receives an event. The bubble on one input terminal of each Muller C-element indicates that initially, after master clear, that element behaves as if an event had already been received.
A request input signal R and an acknowledge output signal A are shown. A request event causes information to propagate down the chain of processing cells and emerge at the right end. The acknowledge signal from each successive Muller C-element enables the previous Muller C-element to receive the next request input signal and propagate that request, in turn, through the chain.
The C-element output signals control latches that sequence the data along the datapath. The rate at which requests and acknowledges propagate through the C-element control circuits determines the rate at which the latches are made opaque and transparent. If this rate is too fast, the datapath cannot keep up and data will be lost. On the other hand, if this rate is too slow, the performance of the system will be low. Therefore, the designer is faced with the tricky task of building a control circuit that has just enough delay so the datapath can keep up, but no more, to try to maximize performance. Because the consequence of too little delay is that the circuit fails, designers must be conservative and provide extra delay. The amount of extra delay required depends on the matching of transistors and therefore is hard to predict at the time the circuit is designed, requiring even more margin. If there were a way to provide an adjustable delay that could be tuned after manufacturing, asynchronous circuits could operate faster because less margin would be required.
SUMMARY OF THE INVENTION
This invention provides an improved control circuit for a FIFO datapath or other use. The improved control circuit is provided with adjustable delay elements between each of the Muller C-elements, enabling each of the output nodes of the control circuit to provide an appropriate control signal in a precise timing relationship with that required by the datapath. In a preferred embodiment, this is achieved by placing an adjustable delay element between the output node of each Muller C-element and the input node of one or both of the subsequent and previous Muller C-elements connected to that output node. By tuning the adjustable delay elements to correspond to the delays inherent in the processing operations in the datapath, higher performance is achieved.
In a preferred embodiment an asynchronous system includes a datapath which has a plurality of stages for performing processing operations on data supplied to them and a control path coupled to the datapath which controls the operation of the datapath. The control path includes adjustable delay elements to enable control of the timing of operations within the control path.
In another preferred embodiment, a sequence of Muller C-elements is provided, with a first element controlling a first output node, a second element controlling a second output node, and a third element controlling a third output node. A first delay element is connected between the first output node and a first input terminal of the second Muller C-element and a second delay element is connected between the second output node and the first input terminal of the third Muller C-element. First, second and third datapath elements are coupled to be controlled by the first, second and third output nodes, respectively.


REFERENCES:
patent: 5553276 (1996-09-01), Dean
patent: 5724562 (1998-03-01), Ishiwaki et al.
patent: 6188262 (2001-02-01), Sutherland
patent: 6211704 (2001-04-01), Kong

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