Datapath architecture for high area efficiency

Details Datapath architecture for high area efficiency Datapath architecture for high area efficiency

2006-05-30

2006-05-30

Phan, Trong (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S063000

Reexamination Certificate

active

07054178

ABSTRACT:
A particular DRAM data path architecture is disclosed. In accordance with this invention, the sharing of MDQ sense amplifiers simplifies the circuit design of the memory sub array. Fewer MDQ sense amplifiers and fewer unique MDQ lines leads to a reduced chip layout area. The high address bit of the word line row address (RA) is used to select a particular main data sense amp by means of a control switch. Not only are the sense amplifiers multiplexed for the new sub array, but the data I/O are multiplexed as well, leading to a significant reduction in the number of circuits required.

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