Boots – shoes – and leggings
Patent
1986-07-15
1989-03-21
Shaw, Gareth D.
Boots, shoes, and leggings
364900, G06F 1300, G06F 1500
Patent
active
048149780
ABSTRACT:
This invention provides a novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of dataflow processing elements communicate externally by means of input/output circuitry, and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions. In accordance with the present invention, these instructions include associations of execution components and enable components identified by instruction indices.
REFERENCES:
patent: 3962706 (1976-06-01), Dennis et al.
patent: 3978452 (1976-08-01), Barton et al.
patent: 4112489 (1978-09-01), Wood
patent: 4128882 (1978-12-01), Dennis
patent: 4130885 (1978-12-01), Dennis
patent: 4145733 (1979-03-01), Misunas et al.
patent: 4149240 (1979-04-01), Misunas et al.
patent: 4153932 (1979-05-01), Dennis et al.
patent: 4156903 (1979-05-01), Barton et al.
patent: 4156908 (1979-05-01), Missios et al.
patent: 4156909 (1979-05-01), Barton et al.
patent: 4156910 (1979-05-01), Barton et al.
patent: 4187539 (1980-02-01), Eaton
patent: 4197589 (1980-04-01), Cornish et al.
patent: 4236206 (1980-11-01), Strecker et al.
patent: 4245299 (1981-01-01), Woods et al.
patent: 4251861 (1981-02-01), Mago
patent: 4254476 (1981-03-01), Burrows
patent: 4271480 (1981-06-01), Vinot
patent: 4390969 (1983-06-01), Hayes
patent: 4413318 (1983-11-01), Herrington
patent: 4447875 (1984-05-01), Bolton et al.
patent: 4467409 (1984-08-01), Potash et al.
patent: 4475156 (1984-10-01), Federico et al.
patent: 4502118 (1985-02-01), Hagenmaier, Jr. et al.
patent: 4591979 (1986-05-01), Iwashita
patent: 4644461 (1987-02-01), Jennings
patent: 4675806 (1987-06-01), Uchida
Jenkins, Richard A., "Supercomputers of Today and Tomorrow", Tab Books Inc., Blue Ridge Summit, Pa., 1986, pp. 92-94.
Reisig, Wolfgang, "Petri Nets", Springer-Verlag, Berlin, Heidelberg, New York, 1982, Chapters 1 and 3.
Hwang, Kai and Briggs, Faye A., "Computer Architecture and Parallel Processing", McGraw Hill, Inc., N.Y., 1984, Sections 10.1 and 10.2.
Ackerman, W. B., Dennis, J. B., VAL--A Value-oriented Algorithmic Language, M.I.T., Cambridge, MA, Jun. 1979.
Cornish, M., The TI Data Flow Architectures: The Power of Concurrency for Avionics, Dataflow Dev. Group of Texas Instruments, Inc., Austin, Texas, Nov. 1979.
Dennis, J. B., Stoy, J. E., Guharoy, B., VIM: An Experimental Multi-user System Supporting Functional Programming, M.I.T., Cambridge, MA, May 1984.
Dennis, J. B., Misunas, D. P., A Preliminary Architecture for a Basic Data Flow Processor, M.I.T., Cambridge, MA, Aug. 1984.
Gao, G. R., An Implementation Scheme for Array Operations in Static Data Flow Computers, M.I.T., Cambridge, MA, May 1982.
Gostelow, A. & Gostelow, K. P., A Computer Capable of Exchanging Processors for Time, University of California, Irvine, California-1977.
Gurd, J. R., Kirkham, C. C., Watson, I., The Manchester Prototype Dataflow Computer, Communications of the ACM, vol. 28, No. 1, Jan. 1985.
Patil, S. S., Closure Properties of Interconnections of Determinate Systems, M.I.T., Cambridge, MA, 1970.
Van Horn, E. C., Computer Design for Asynchronously Reproducible Multiprocessing, M.I.T., Cambridge, MA, Nov. 1966.
Watson, I. & Gurd, J., A Practical Data Flow Computer, University of Manchester, Manchester, England, Feb. 1982.
Yuba, T., Shimada, T., Hiraki, K. and Kashiwagi, H., A Dataflow Computer for Scientific Computations, Electrotechnical Laboratory, 1-1-4 Umesono, Sekyramura, Niiharigun, Ibaraki 305, Japan-1984.
Ackerman, W. B., Data Flow Languages, MIT CSG Memo 177-1, M.I.T. Cambridge, Mass., May 1979.
Ackerman, W., Bauman, H., Woodhall, B., Static Data Flow Cell Block, M.I.T. CSG Memo 232, Nov. 4, 1983.
Ackerman, W. B., The VAL Intermediate Graph Format, M.I.T. CSG Memo 235, Jan. 12, 1984.
Adams, G. B., III, et al, Report on an Evaluation Study of Data Flow Computation, Research Inst. for Advanced Computer Science, NASA, Apr., 1985.
Arvind, Kathail, V., A Multiple Processor Dataflow Machine, MIT CSG Memo 205-1, Feb. 1981.
Arvind, Functional Languages and Architecture, Progress Report for 1983-1984, M.I.T., Dec. 8, 1984.
Arvind, Ianucci, R. A., Two Fundamental Issues in Multiprocessing; The Da taflow Solution, M.I.T. CSG Memo 226-2, Jul. 27, 1983.
Tam-Auh Chu, The Design, Implementation and Testing of a Self-Timed Two by Two Routes, M.I.T. CSG Memo 236, Feb. 1983.
Dennis, J. B., Dataflow Ideas for Supercomputers, Proceedings of the Comp. Con. '84, 28th IEEE Computer Soc. Int., Feb. 27-Mar. 1, 1984.
Dennis, J. B., Progress Report 1979-80, MIT CSG Memo 203, Feb. 1981.
Dennis, J. B., Data Flow Supercomputers, M.I.T., Cambridge, Mass., Nov. 1980.
Dennis, J. B., High Performance Dataflow Computers, M.I.T. Cambridge, Mass., CSG Memo 215, Mar. 1982.
Dennis, J. B. et al., The MIT Dataflow Engineering Model, M.I.T., Cambridge, Mass., CSG Memo 222, Nov. 1982.
Dennis, J. B., Data Flow Models of Computation, International Summer School on Control Flow and Dataflow; Markteberdorf, Germany, Aug. 1984.
Dennis, J. B., Rong, Gao Guang, Maximum Pipelining of Array Operations on Static Data Flow Machine, M.I.T. CSG Memo 233, Sep. 1984.
Dennis, J. B., An Operational Semantics for a Language with Early Completion Data Structures, MIT CSG Memo 207, Nov. 23, 1984.
Dennis, J. B., Computational Structures Progress Report for 1983-1984, M.I.T. CSG Memo 246, Feb. 28, 1985.
Gao, G. R., A Maximally Pipelined Tridiagonal Linear Equation Solver, M.I.T. CSG Memo 254, Jun. 1985.
McGraw, J. R., Data Flow Computing-The VAL Language, M.I.T., Cambridge, Mass., CSG Memo 188, Jul. 1980.
Montz, L., Safety & Optimization Transformation for Dataflow Programs, M.I.T., Feb. 1980.
NEC Electronics, Inc., .mu.PD 7281 Image Pipelined Processor, Feb. 1985.
Plas, A., et al, Lau System Architecture: A Parallel Data Driven Processor Based on Single Assignment, Univ. de Toulouse, France, 8/8/76.
Rodriguez, J. E., A Graph Model for Reproduction, M.I.T., Laboratory for Computer Science, Sep. 1969.
Rumbaugh, J. E., A Parallel Asynchronous Computer Architecture for Data Flow Programs, M.I.T., Cambridge, Mass., May 1975.
Vedder, R. et al, The Hughes Data Flow Multiprocessor, Hughes Aircraft Co., Box 902, El Segundo, CA, 1985.
Altman Gerald
Dataflow Computer Corporation
Ruiz Adolfo L.
Shaw Gareth D.
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