Data write pulse compensator circuit

Details Data write pulse compensator circuit Data write pulse compensator circuit

1990-08-22

1991-10-22

Canney, Vincent P.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

360 46, G11B 509

Patent

active

050600893

ABSTRACT:
The data write pulse compensator circuit functions to produce an erase frequency that is greater than twice the data frequency using a single clock source to thereby improve the signal to noise ratio in the read back signal. This apparatus uses a precision delay line to produce a series of clock signals with each successively replicated clock signal being delayed a predetermined amount of time with respect to the last previously replicated clock signal. The plurality of generated and delayed clock signals is then combined by a programmable pulse synthesizer to produce a data pulse of a predetermined frequency and width. The same apparatus is also used to produce a pair of erase pulses using a different combination of the delayed replicated clock signals to produce a pulse identical in size and shape to that produced for the data frequency. However, the erase pulses are time shifted such that their apparent frequency is greater than twice the data frequency.

REFERENCES:
patent: 4896337 (1990-01-01), Bushy, Jr.
patent: 4964107 (1990-10-01), Galbraith et al.

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