Data wire of sub-pixel matrix array display device

Details Data wire of sub-pixel matrix array display device Data wire of sub-pixel matrix array display device

2002-06-27

2004-12-28

Chowdhury, Tarifur R. (Department: 2871)

Liquid crystal cells, elements and systems

Particular excitation of liquid crystal

Electrical excitation of liquid crystal

C349S106000, C349S108000, C349S152000

Reexamination Certificate

active

06836300

ABSTRACT:

The present invention claims the benefit of Korean Patent Application No. P2001-62994 filed in Korea on Oct. 12, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data wire device of a display device, and more particularly, to a data wire device for supplying data to the pentile matrix display device.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device controls a transmittance due to change arrangement of liquid crystal layer using an electric field to display image data (a picture). The LCD device includes a liquid crystal panel where liquid crystal cells are arranged in a matrix configuration, and a driving circuit for driving the liquid crystal panel.
FIG. 1
is a block diagram of an LCD device according to the conventional art. In
FIG. 1
, the LCD device includes a liquid crystal panel
2
with liquid crystal cells arranged in a matrix configuration, a gate driver
4
for driving gate lines GL
0
to GLn of the liquid crystal panel
2
, a data driver
6
for driving data lines DL
1
to DLm of the liquid crystal panel
2
, a gamma voltage generator
8
for supplying gamma voltage to the data driver
6
, and a timing controller
10
for controlling the gate driver
4
and the data driver
6
.
The timing controller
10
responds to clock signals and horizontal and vertical synchronous signals received from other circuitry to control driving timing of the gate driver
4
and the data driver
6
. Specifically, the timing controller
10
responds to the clock signals and the horizontal and vertical synchronous signals, and generates gate shift clock signals GSC and gate start pulses GSP to control the driving timing of the gate driver
4
. In addition, the timing controller
10
responds to input clock signals and the horizontal and vertical synchronous signals, and generates data clock signals, data control signals, and polarity control signals to control the driving timing of the data driver
6
. At the same time, the timing controller
10
is synchronized with the data clock signals and supplies video input data of red, green, and blue color to the data driver
6
.
The gate driver
4
supplies a gate high voltage to the gate lines GL
1
to GLn corresponding to a scanning period
1
H to drive thin film transistors TFTs of the liquid crystal panel
2
, and supplies a gate low voltage during a rest period. In addition, the gate driver
4
supplies a gate low voltage to a top gate line GL
0
that forms an electrode of a storage capacitor of a first scanning line. The data driver
6
converts a digital data signal received from the timing controller
10
to an analogue data signal, and supplies data signals of 1 horizontal line portion to the data lines DL
1
to DLm every one horizontal period
1
H when the gate high voltage is supplied to the gate lines GL
1
to GLn.
The gamma voltage generator
8
supplies a gamma voltage to the data driver
6
, wherein the gamma voltage is predetermined to have different levels from one another in accordance with the voltage level of the data signal. The conversion by the data driver
6
of the digital data signal to the analogue data signal makes use of the gamma voltage to compensate gamma characteristics in the LCD device. In addition, the data driver
6
reverses polarity of the data signals supplied to the data lines DL
1
to DLm in accordance with the polarity control signal received from the timing controller
10
. Accordingly, when the liquid crystal panel
2
is driven by a Dot Inversion Method, the data driver
6
supplies data signals having a polarity contrary to the data signals that are supplied to adjacent liquid crystal cells in vertical and horizontal directions to each of liquid crystal cells. In addition, the data driver
6
reverses the polarity of the data signals supplied to all the liquid crystal cells on the liquid crystal panel during each frame.
The liquid crystal panel
2
includes liquid crystal cells arranged in a matrix configuration, thin film transistors TFTs formed at intersections of the gate lines GL
0
to GLn and the data lines DL
1
to DLm. Each of the thin film transistors TFTs respond to the gate high voltage transmitted along the gate lines GL
1
to GLn, and supplies data signals transmitted along the data lines DL
1
to DLm to the liquid crystal cells. Each of the liquid crystal cells can equivalently be displayed as a liquid crystal capacity capacitor CLC including a pixel electrode connected to the TFT and a common electrode facing each other with a liquid crystal material disposed therebetween. In additional, a storage capacitor Cst is provided for sustaining the data voltage charged at the liquid crystal capacity capacitor CLC in the liquid crystal cell until the next data voltage is charged, i.e., while the gate low voltage is applied. The storage capacitor Cst is formed between the previous gate line and the pixel electrode.
FIG. 2
is plane view of a liquid crystal cell of the liquid crystal panel shown in
FIG. 1
according to the conventional art. In
FIG. 2
, a pixel electrode is provided within each cell area provided at intersections of the gate lines GL
1
to GL
3
and the data lines DL
1
to DL
4
. The pixel electrode
9
is connected to a corresponding one of the data lines DL
1
to DL
4
via source and drain electrodes
5
and
7
of the TFT
1
, and a gate electrode
3
of the TFT
1
is connected to one of the gate lines GL
1
to GL
3
. A storage capacitor
11
is formed within an overlapping area of the corresponding pixel electrode
9
and a previous one of the gate lines GL(i−1). Data signals corresponding to one of red R, green G, and blue B color filters for color display are supplied to each of the data lines DL
1
to DL
4
. Each of the red, green, and blue color filters are formed on an upper substrate corresponding to the cell area where the pixel electrode
9
is formed, and a common electrode is formed upon the color filters for supplying a reference voltage to an underlying liquid crystal material layer. Each pixel of the liquid crystal cells may be expressed by a combination of red R, green G, and blue B sub-pixels arranged in parallel. A plurality of contact pads (not shown) are provided along an edge area of the liquid crystal panel to electrically contact output terminals of the gate driver and the data driver, which are manufactured as IC chips through a Tape Carrier Package. Each of the plurality of contact pads are formed to correspond in a one-to-one relationship with the gate lines and the data lines on the liquid crystal panel.
FIG. 3
is a plane view of data pads connected to the data lines shown in
FIG. 2
according to the conventional art. In
FIG. 3
, data pads DP are connected to data lines DL through data links DLK. The data pads DP, which are connected to the tape carrier package with the data drive IC chip, are disposed with relatively narrow gaps for contacting with output pads of the tape carrier package. Conversely, the data lines DL that are formed within a picture display area are disposed with relatively wide gaps. Accordingly, the data pads DP, the data lines DL, and the data links DLK are formed as a body.
FIG. 4
is a cross-sectional view of the data pad shown in
FIG. 3
along I—I according to the conventional art. In
FIG. 4
, a source/drain electrode layer
16
is formed on a gate insulating film
14
of a lower substrate
12
. The lower substrate
12
includes a data pad DP portion, a data link DLK portion, and a data line DL portion. A protective film
18
is formed on the source/drain electrode layer
16
, and is patterned to form a contact hole within an area where the data pad DP portion is located. In addition, a pad terminal electrode
20
made of a transparent electrode material is formed together with the pixel electrode of the picture display area, and electrically contacts the data pad DP portion of the source/drain electrode layer
16
.
However, the LCD device according to the conventional art is problematic. With the

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