Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2002-05-07
2004-02-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S175000
Reexamination Certificate
active
06690217
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data width corrector for correcting the data width of receive data to obtain an appropriate data width when the data is input from outside.
FIG. 10
illustrates a conventional data width corrector (disclosed in Japanese Laid-Open Patent Publication No. 2000-183731). In this data width corrector, data width correction is performed by a duty compensation circuit
51
, which includes a slice amplifier SAMP, average detectors AVD
1
and AVD
2
, and a differential amplifier DAMP. The slice amplifier SAMP compares received differential data with a reference potential and outputs logical “0” and “1” sequentially. The average detectors AVD
1
and AVD
2
respectively calculate time averages of complementary signals output from the amplifier SAMP. The differential amplifier DAMP compares average signals from the average detectors AVD
1
and AVD
2
and changes the reference potential for the slice amplifier SAMP.
In a high-speed signal, in which the pulse rise and fall times are never negligible, a deviation of duty is expressed as a deviation of a cross point as shown in
FIGS. 11A
to
11
C. The duty of such a signal can be 100% recovered by performing slice amplification focusing on the voltage at the cross point.
To state more specifically, in the duty compensation circuit
51
, the average detectors AVD
1
and AVD
2
respectively calculate averages of the forward and reverse outputs of the slice amplifier SAMP, and the center voltage at a slice is feedback-controlled so that the averages match with each other. In this way, signals with 100% duty can be output from the two outputs of the slice amplifier SAMP. In other words, by calculating the difference between the averages of the forward and reverse outputs in the differential amplifier DAMP and setting the difference as a slice voltage for the slice amplifier SAMP, the duty of data signals output from the duty compensation circuit
51
can be made close to 100%.
However, the conventional data width corrector described above has the following problem. The duty compensation circuit
51
performs duty correction by setting the reference potential with respect to the cross point. Therefore, for data as shown in
FIG. 12
, for example, in which cross points have already deviated at the time of input, duty correction or correction for obtaining an appropriate data width is significantly difficult. In reality, the data width is widened or narrowed in some cases due to the properties of a transmitter driver, jitter on a transmission route, mismatch of an internal circuit of a receiver LSI and the like.
SUMMARY OF THE INVENTION
An object of the present invention is providing a data width corrector capable of adjusting the data width appropriately even for data in which cross points have already deviated at the time of input.
The data width corrector of the present invention includes: an input circuit for receiving a differential signal from outside, changing the differential signal to single-phase receive data, and outputting the receive data; a determination circuit for determining whether or not the HIGH period or the LOW period of the receive data is appropriate; and an adjustment circuit for adjusting duty of the receive data to make the HIGH period or the LOW period of the receive data appropriate based on the determination results from the determination circuit.
According to the invention described above, the determination circuit determines whether or not the HIGH period or the Low period of the receive data output from the input circuit is appropriate. The adjustment circuit adjusts the duty or the data width of the receive data to make the HIGH period or the LOW period appropriate. By this adjustment, the receive data becomes close to a desired data width, and this increases the margin used when the receive data is latched. In other words, the data width can be appropriately adjusted even for data in which cross points have already been deviated at the time of input.
Note that since data is not necessarily a repetition pattern of “0” and “1” as a clock is, the “duty ” as used herein refers to a deviation of the width of “0” and “1” with respect to a desired data width.
Preferably, the determination circuit of the data width corrector described above compares the average time of the HIGH period or the LOW period between a reference signal input from outside and the receive data, and makes determination based on the comparison results.
With the above configuration, if noise is locally generated in the input data, it can be minimized by calculating time averages. Therefore, further appropriate determination is possible in the determination circuit.
Preferably, the reference signal is a clock signal having substantially the same frequency as the differential signal, and the determination circuit performs the determination within a predetermined period during which the differential signal is a clock signal pattern.
With the above configuration, the clock signal used for latching of the receive data can be used as the reference signal. Since an LSI for communication normally generates such a clock signal internally, no separate generation of the reference signal is required. Thus, this provides advantageous circuit configuration.
The reference signal is preferably a latch signal obtained by latching the receive data with a clock signal having substantially the same frequency as the differential signal.
With the above configuration, when the receive signal is latched with a clock signal having substantially the same frequency as the input differential signal, the data width of the resultant latch signal is restricted by the clock signal, providing a desired data width. Therefore, by using the latch signal as the reference signal, the data width of the receive data can be appropriately corrected. Moreover, this use of the latch signal eliminates the necessity of providing the predetermined period for input of a clock signal pattern, and thus data width correction is possible in real time.
Preferably, the data width corrector of the present invention further includes a frequency detector for detecting the difference in frequency between the differential signal and the clock signal, and the determination circuit halts the determination when the difference in frequency detected by the frequency detector exceeds a predetermined amount.
With the above configuration, adjustment of the data width is made when the frequency of the reference signal is sufficiently close to the frequency of the differential signal. Therefore, occurrence of an error in data width adjustment is prevented.
Preferably, the data width corrector of the present invention further includes a transition detector for detecting the number of times of transition of the receive data, and the determination circuit halts the determination when the number of times of transition detected by the transition detector exceeds a predetermined number.
With the above configuration, the data width adjustment is made only when the number of times of transition of the receive data is equal to or more than a predetermined number, that is, when comparison of the average time of the HIGH period or the LOW period is useful. Therefore, occurrence of an error in data width adjustment is prevented.
Preferably, the determination circuit of the data width corrector described above includes first and second comparison sections for determining which is greater in the average time of the HIGH period, the reference signal or the receive data and which is greater in the average time of the LOW period, the reference signal or the receive data, respectively, and the determination circuit halts the determination and holds the setting in the adjustment circuit when the determination results obtained by the first and second comparison sections match with each other.
With the above configuration, no data width correction of the receive data is performed when the determination results on the average times of the HIGH period and the LOW period match w
Callahan Timothy P.
Cox Cassandra
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