Data transmitter with sequential serialization

Details Data transmitter with sequential serialization Data transmitter with sequential serialization

1999-12-20

2003-12-16

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

C375S220000

Reexamination Certificate

active

06665360

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for data transmission with sequential serialization generally and, more particularly, to a method of data transmission that may improve efficiency and precision.
BACKGROUND OF THE INVENTION
A transceiver is a device that implements a transmitter and a receiver. The efficiency and precision of a transceiver device is significantly dependent on the transmitter implementation.
Referring to
FIG. 1
, a block diagram illustrating a conventional transmitter
10
is shown. The transmitter
10
may be implemented as part of a transceiver device. The transmitter
10
comprises a full rate phase-locked loop
12
, a bit rate counter
14
, a high speed shifter
16
and an input register
18
. The transmitter
10
has high power consumption due to the implementation of the full rate phase locked loop
12
, the high speed counter
14
and the high speed shifter
16
.
Referring to
FIG. 2
, a block diagram of a second conventional transmitter
10
′ is shown. The transmitter
10
′ may be implemented as part of a transceiver device. The transmitter
10
′ comprises a 1/T rate phase-locked loop
12
′, a select generator
15
, a multiplexer output block
17
and an input register
18
′. The transmitter
10
′ has lower power consumption than the transmitter
10
due to parallel operation. However, the transmitter
10
′ suffers from jitter injected due to a mismatch in the select generator
15
. Jitter is additionally injected due to a mismatch between the large number of stages in the multiplexer output block
17
.
Referring to
FIG. 3
, a circuit diagram of a third conventional transmitter
10
″ is shown. The transmitter
10
″ may be implemented as part of a transceiver device. The transmitter
10
″ comprises a plurality of 2 to 1 multiplexers
20
a
-
20
n,
a first plurality of D-type flip-flops
22
a
-
22
n
and a second plurality of D-type flip-flops
24
a
-
24
n.
The transmitter
10
″ implements two half rate shift registers groups (i) the flip-flops
22
a
-
22
n
and (ii) the flip-flops
24
a
-
24
n
(as opposed to one full rate shift register). The power consumption of this method is still unnecessarily high, since the serial shift can be avoided.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) a first control signal, (ii) a second control signal, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal. The second circuit may be configured to generate one or more intermediate data signals operating at a second speed in response to (i) the first control signal, (ii) the one or more first clock signals and (iii) the first data signal. The third circuit may be configured to generate an output data signal operating at a third speed in response to (i) the second control signal and (ii) the one or more intermediate data signals.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) reduce power consumption, (ii) reduce jitter by minimizing the number of parallel elements, (iii) reduce jitter resulting from a mismatch between parallel elements, (iv) allow a single VCO phase to control serialization and/or (v) reduce mismatch issues related to one or more control signals.


REFERENCES:
patent: 4644346 (1987-02-01), Ito et al.
patent: 5572721 (1996-11-01), Rostamian
patent: 5602882 (1997-02-01), Co et al.
patent: 5668830 (1997-09-01), Georgiou et al.
patent: 5905388 (1999-05-01), Van Der Valk et al.
patent: 2002/0114416 (2002-08-01), Enam et al.
A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis, by Alan Fiedler et al., ISSCC97/Session 15/Serial Data Communications/Paper FP 15.1, 1997, pp. 238-239, 464.
A 2.125-Gb/s BiCMOS Fiber Channel Transmitter for Serial Data Communications, by Muneo Fukaishi et al., IEEE Journal of Sold-State Circuits, vol. 34, No. 9, Sep. 1999, pp. 1325-1329.

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