Data transmission system employing clock-enriched data...

Details Data transmission system employing clock-enriched data... Data transmission system employing clock-enriched data...

1999-11-12

2001-08-07

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

Reexamination Certificate

active

06271777

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to data transmission systems and, more particularly, to such systems employing clock-enriched data coding on a transmission side and sub-harmonic de-multiplexing on a receiver side.
BACKGROUND OF THE INVENTION
It is common for serial data links to be constructed from subsidiary data streams at a lower rate. This so-called time division multiplexing requires a method for de-multiplexing data at the receiver which in turn requires timing information. For binary data transmission, this clock recovery operation is commonly done at the serial data frequency of the transmission system, e.g., the recovered clock frequency matches the serial transmission rate. These operations are currently done using nonlinear circuit elements and phase-locked-loop (PLL) techniques, or high-Q filters, as described in A. Buchwald, K. Martin, “Integrated Fiber-Optic Receivers,” Kluwer, 1995, ISBN0-7923-9549-2 and “Monolithic phase locked loops and clock recovery circuits,” Behzad Razavi (ed.) IEEE press, 1996, the disclosures of which are incorporated herein by reference. Such methods are complex and require high speed circuitry.
Therefore, it would be highly desirable to provide methods and apparatus for providing clock-enriched data coding at a transmitter end of a data transmission system and sub-harmonic de-multiplexing at a receiver end of the system in order to overcome the shortcomings of the prior art, as mentioned above and which otherwise exist in the art.
SUMMARY OF THE INVENTION
In the present invention, we provide for the addition of timing information to the transmitted data stream such that the use of high speed PLLs and high Q filters, as well as nonlinear circuit elements preceding them, can be avoided. Furthermore, by extracting timing information at a frequency less than that of the serial data transmission frequency in accordance with the invention, the circuit elements that are employed need not operate at this high frequency, but at the lower rate of the subsidiary data streams, thereby yielding further simplification. Simplification of the receiver typically yields manufacturing and operational cost savings. Thus, as will be explained, the present invention provides methods and apparatus for clock-enriched data coding at a transmitter end of a data transmission system and sub-harmonic de-multiplexing at a receiver end of the data transmission system.
In one aspect of the invention, a method for use in a data transmission system comprises the steps of: (i) adding timing information to a serial data stream; (ii) recovering the timing information from the serial data stream to generate a plurality of clock signals associated with the timing information, each clock signal having a common frequency and a different phase associated therewith, the common frequency being less than a frequency associated with the serial data stream; and (iii) converting the serial data stream to a plurality of parallel data streams respectively using the plurality of clock signals.
The timing information may be added to the serial data stream at a data transmitter portion of the system. The invention provides for various ways to add the timing information to the serial data stream, i.e., enrich the serial data stream with the timing information. In one embodiment, a transmission code used to encode the data stream may be modified to insert a transition bit pattern in a given code sequence, wherein the transition bit pattern corresponds to the timing information. In another embodiment, a code character may be inserted between code sequences, wherein the code character corresponds to the timing information. In the two embodiments above, the transition bit patterns and code characters preferably give rise to one or more sub-harmonic clock tones in the serial data stream. In yet another embodiment, the timing information may be inserted directly into the serial data stream, as a discrete clock tone. It is appreciated that in a preferred embodiment the timing information added in the form a clock signal has a well-defined (e.g., phase-locked) relationship to the transmitted data. This is because a preferred method for inserting the timing information utilizes the same clock frequency used to generate the multiplexed data stream, and thereby is necessarily phase-locked to the transmitted data. Once recovered, then, the receiver need only perform a phase alignment operation on the received clock signal.
Recovery of the timing information, e.g., clock tones, may be performed via filtering and phase aligning the timing information to generate the plurality of clock signals. Conversion of the serial data stream to the plurality of parallel data streams may then include using the clock signals to respectively sample or de-multiplex the serial data stream to yield the plurality of parallel data streams. It is to be appreciated that the plurality of parallel data streams may also have a frequency that is less than the frequency associated with the serial data stream.
Advantageously, the inventive techniques described herein allow a receiver circuit to use lower speed components, or at least fewer high speed components, thereby significantly reducing design parameters such as, for example, power, size, and cost. Similarly, in an integrated circuit embodiment, the invention also provides significant reduction in, for example, power, size and cost requirements. In one embodiment, the invention may be implemented in accordance with a fiber optic data transmission system.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5644418 (1997-07-01), Woodward
patent: 6097323 (2000-08-01), Koga
patent: 6121906 (2000-09-01), Kim
C-K Yang et al., “A 0.8-&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links,” IEEE Journal of Solid-State Circuits, vol. 31, No. 12, pp. 2015-2023, Dec. 1996.

Affiliated with

Also associated with

Rating

Data transmission system employing clock-enriched data... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data transmission system employing clock-enriched data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transmission system employing clock-enriched data... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2497670