Static information storage and retrieval – Magnetic bubbles – Guide structure
Patent
1997-08-12
1999-04-06
Dinh, Dung C.
Static information storage and retrieval
Magnetic bubbles
Guide structure
365221, 36518905, 36518901, 370539, 370541, 375356, G06F 700
Patent
active
058929207
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND
The present invention generally relates to data transmission with speeds of the order of magnitude of several Gigabits/sec between two clock domains, of which each may be constituted by e.g. a CPU, a part of an ATM switch or other equipment which sends and receives data. ATM allows transmission of large data quantities over arbitrary media with the use of data packages with a prescribed length and small overhead.
More specifically, the invention relates to a data transmission system, in which data streams are to be transmitted at a large speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds.
In two data transmission systems, which are operating with approximately the same clock frequency generated by two separate oscillators, one in each system, and which are to be connected and transmit data to each other, a certain drift may occur between the frequencies. Because of this a buffer must be inserted between the two systems, which may emit data faster than it receives it, or vice versa, depending on which system's clock frequency is the larger one.
In the U.S. Pat. No. 5,305,253 a memory with separate read and write buses, two address ring counters, one for write and one for read operations, and an alarm which detects when the buffer is empty and full, is described. Since it is very difficult to make memories with a reply time shorter than 7 ns without resorting to the use of GA, this solution is not usable at frequencies of the order of magnitude of Gigabits/sec.
In the U.S. Pat. No. 4,819,201 an asynchronous FIFO circuit is described which includes consecutive data storage registers, which relay incoming data if the following register is empty. When the FIFO circuit is empty data will accordingly be let through from the beginning of the register stack to its end. This may cause risk for degradation of data and is furthermore a slow solution.
Among other publications relating to the same subject, the following may be mentioned.
U.S. Pat. No. 5,319,597 "FIFO memory and line buffer",
U.S. Pat. No. 5,084,837 "FIFO buffer with folded data transmission path permitting selective bypass of storage",
U.S. Pat. No. 4,803,654 "Circular first-in, first-out buffer system for generating input and output addresses for read/write memory independently".
SUMMARY
An object of the present invention is to provide a fast, small and simple data buffer between the two clock domains in the data transmission system defined above by way of introduction.
This is achieved according to the invention through a data buffer, which includes a number of data storage elements, a tree shaped structure of multiplexer elements, a write address generator and a read address generator. The data storage elements have data inputs connected in parallel to an input for a data stream from the sending clock domain. The tree shaped structure of multiplexer elements is arranged to receive data from the data storage elements, and emits on an output a data stream to the receiving clock domain. The write address generator generates, controlled by a write clock signal from the clock of the sending clock domain, read addresses for entering data from the sending clock domain into the data storage elements, one at a time. The read address generator generates, controlled by a read clock signal from the clock generator of the receiving clock domain, read addresses for reading out data from the data storage elements in the same order as they were entered.
The tree shaped structure can have a first level of multiplexer elements connected to receive data in parallel from each of a number of the data storage elements. A number of following levels of storage elements are connected to receive data from a number of the multiplexer elements of the previous level. A last level includes a multiplexer element, on the output of which a data stream is emitted to the receiving clock domain.
More specifically, the multiplexer elements of the first level can each be connected to receive data from at le
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Arvidsson Carl-Erik
Lindblom Martin
Dinh Dung C.
Le Hieu
Telefonaktiebolaget LM Ericsson
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