Data transmission system between a main CPU board having a wait

Details Data transmission system between a main CPU board having a wait Data transmission system between a main CPU board having a wait

1986-02-18

1989-05-16

Zache, Raulfe B.

Boots, shoes, and leggings

379165, 34082552, 34082503, 3642223, 3642421, 3642601, 364284, G06F 1338, G06F 1342

Patent

active

048315168

ABSTRACT:
A data transmission system between a main CPU and a plurality of sub-CPU's includes a data bus connected between them, a CPU select line for transmitting a CPU select signal from the main CPU to the sub-CPU's, a latch circuit for providing a wait signal to the main CPU upon write or read in the main CPU with respect to the sub-CPU's and a wait clear line connected between the respective CPU's to provide to the latch circuit a wait clear signal upon completion of input and output of the sub-CPU to release the waited state of the main CPU, the transmission system being thereby simplified to reduce installation space and wiring labor.

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patent: 4506324 (1985-03-01), Healy
patent: 4590556 (1986-05-01), Berger et al.
patent: 4660219 (1987-04-01), Tanaka et al.

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