Pulse or digital communications – Cable systems and components
Reexamination Certificate
1999-02-09
2001-11-13
Chin, Stephen (Department: 2734)
Pulse or digital communications
Cable systems and components
Reexamination Certificate
active
06317465
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission system for accomplishing differential transmission of each of a plurality of data bits.
Against the background of an enormous amount of dynamic image data to be processed, high-speed data transmission between a plurality of semiconductor integrated circuits mounted on a printed wiring board has been in increasing demand. To satisfy the demand, a Rambus standard and a SyncLink standard have been known in the field of DRAM (dynamic random access memory) development as standards for clock-synchronized high-speed I/O interfaces. The former standard has been developed by Rambus, Inc. and adopts an open-drain interface. The latter standard has been proposed by JEDEC (Joint Electron Device Engineering Council) and adopts a low-amplitude interface termed a SSTL (stub series terminated transceiver logic) interface.
Each of the conventional I/O interface standards mentioned above has been devised to transmit one data bit over a single data line. Such a single-ended transmission scheme has the drawback of susceptibility to external noise.
There has conventionally been known differential data transmission which is excellent in common-mode noise rejecting performance. The differential data transmission accomplishes the transmission of one data bit by using a pair of data lines. However, if each of a plurality of data bits is to be differentially transmitted between semiconductor integrated circuits on a printed wiring board, the number of lines required is doubled compared with the number of wires used in the foregoing single-ended transmission scheme. As a result, the problems occur that the wiring region occupies a larger area of the surface of the printed wiring board and that a package for the semiconductor integrated circuit should have an increased number of pins.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to reduce the number of lines required to accomplish differential transmission of each of the plurality of data bits.
To attain the object, the present invention accomplishes differential transmission of each of two data bits via three lines, of which one is a first data line, another is a second data line, and the remaining one is a reference line. When the two data bits to be transmitted have different values, the reference line is not used and the second data line serves as a transmission path complementary to the first data line, while the first data line serves as a transmission path complementary to the second data line. When the two data bits to be transmitted have equal values, a voltage representing a value obtained by inverting each of the first and second data bits is supplied to the reference line such that the reference line serves as a transmission path complementary to each of the first and second data lines.
Specifically, a first data transmission system according to the present invention is a data transmission system for differential transmission of each of first and second data bits, the system comprising: a transmitting unit for transmitting the first and second data bits; a receiving unit for receiving the first and second data bits; and a first data line, a second data line, and a reference line each disposed between the transmitting unit and the receiving unit. Moreover, the transmitting unit has the functions of: when the first and second data bits have different values, supplying a voltage representing the value of the first data bit onto the first data line and a voltage representing the value of the second data bit onto the second data line such that the second data line serves as a transmission path complementary to the first data line and that the first data line serves as a transmission path complementary to the second data line; and when the first and second data bits have equal values, supplying a voltage representing each of the values of the first and second data bits onto each of the first and second data lines and a voltage representing a value obtained by inverting each of the first and second data bits onto the reference line such that the reference line serves as a transmission path complementary to each of the first and second data lines.
To attain the foregoing object, the present invention also accomplishes differential transmission of each of two data bits with three lines of another type. One of the three lines is a first data line, another one thereof is a second data line, and the remaining one thereof is a complementary data line. The voltage representing the value of the first data bit is supplied to the first data line. The voltage representing the value of the second data bit is supplied to the second data line. The voltage representing a value obtained by inverting the first data bit is supplied onto the complementary data line. The first data line and the complementary data line are used for differential transmission of the first data bit. When the first and second data bits have different values, the second and first data lines are used for differential transmission of the second data bit. When the first and second data bits have equal values, the second data line and the complementary data line are used for differential transmission of the second data bit.
Specifically, a second data transmission system according to the present invention is a data transmission system for differential transmission of each of first and second data bits, the system comprising: a transmitting unit for transmitting the first and second data bits; a receiving unit for receiving the first and second data bits; and a first data line, a second data line, and a complementary data line each disposed between the transmitting unit and the receiving unit. Moreover, the transmitting unit has the functions of supplying a voltage representing a value of the first data bit onto the first data line, supplying a value of the second data bit onto the second data line, and supplying a voltage representing a value obtained by inverting the first data bit onto the complementary data line. On the other hand, the receiving unit has the functions of determining the value of the first data bit through a comparison between a voltage on the first data line and a voltage on the complementary data line and determining the value of the second data bit through a comparison between the voltage on the first data line and a voltage on the second data line when the respective voltages on the first and second data lines are different from each other and through a comparison between the voltage on the complementary data line and the voltage on the second data line when the respective voltages on the first and second data lines are equal to each other.
REFERENCES:
patent: 4280221 (1981-07-01), Chun et al.
patent: 4423506 (1983-12-01), Kawasaki et al.
patent: 4539680 (1985-09-01), Boudon et al.
patent: 4642805 (1987-02-01), Dumas et al.
Akamatsu Hironori
Yamauchi Hiroyuki
Chin Stephen
Harness & Dickey & Pierce P.L.C.
Jiang Lenny
Matsushita Electric - Industrial Co., Ltd.
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