Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Patent
1997-08-01
1999-12-28
Nguyen, Chau
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
370537, 370542, H04J 306
Patent
active
06009107&
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND
The present invention generally relates to data transmission with speeds of an order of magnitude of several Gigabits/sec between two clock domains, of which each may be constituted by e.g. a CPU, a part of an ATM switch or other equipment which sends and receives data. ATM allows transmission of large data quantities over arbitrary media with the use of data packages with a prescribed length and small overhead.
More specifically, the invention relates to a data transmission system, in which data streams are to be transmitted at a large speed between a sending clock domain and a receiving clock domain, which work with mutually different clock speeds.
In two data transmission systems, which are working with approximately the same clock frequency generated by two separate oscillators, one in each system, and which are to be connected and transmit data to each other, a certain drift may occur between the frequencies. Because of this a buffer must be inserted between the two systems, which may emit data faster than it receives it, or vice versa, depending on which system's clock frequency is the larger one.
In the U.S. Pat. No. 5,305,253 a memory with separate read and write buses, two address ring counters, one for write and one for read operations, and an alarm which detects when the buffer is empty and full, is described. Since it is very difficult to make memories with a reply time shorter than 7 ns without resorting to the use of GA, this solution is not usable at frequencies of the order of magnitude of Gigabits/sec.
In the U.S. Pat. No. 4,819,201 an asynchronous FIFO circuit is described which includes consecutive data storage registers, which forward arriving data if the following register is empty. When the FIFO circuit is empty data will accordingly be let through from the beginning of the register stack to its end. This may cause risk for degradation of data and is furthermore a slow solution.
Among other publications relating to the same subject, the following may be mentioned.
U.S. Pat. No. 5,319,597 "FIFO memory and line buffer",
U.S. Pat. No. 5,084,837 "FIFO buffer with folded data transmission path permitting selective bypass of storage",
U.S. Pat. No. 4,803,654 "Circular first-in, first-out buffer system for generating input and output addresses for read/write memory independently".
SUMMARY
A main object of the invention is, for a data transmission system of above defined art, to provide an improved buffer between two clock domains which are working with different clock speeds. This buffer shall be designed so that its way of working saves energy and simplifies operation at high frequencies, and so that no clock signal will have to be distributed over said buffer as a whole.
According to a first aspect the data transmission system according to the invention comprises a first system part circuit for receiving from the first clock domain a data stream having the clock speed of the first clock domain. The first system part circuit is controlled by this clock speed for serial/parallel converting the data stream to parallel data streams having each a clock speed being a certain fraction of the clock speed of the first clock domain. A second system part circuit receives the parallel data streams and is controlled by the clock speed of the second clock domain for parallel/serial converting them to an output data stream to the second clock domain having the clock speed of the second clock domain.
The first system part circuit may include an input node having a data input for the data stream from the sending clock domain, a control input for a clock signal representing the clock speed of the sending clock domain, data outputs for output data streams, and a first serial/parallel converter circuit for receiving the data stream and the clock signal for converting, controlled by the latter, the input data stream to the parallel data streams having each said clock speed fraction.
A first clock dividing circuit may be provided for converting, for each of the output data streams, the clock sign
REFERENCES:
patent: 4803654 (1989-02-01), Rasberry et al.
patent: 4819201 (1989-04-01), Thomas et al.
patent: 5084837 (1992-01-01), Matsumoto et al.
patent: 5132970 (1992-07-01), Urbansky
patent: 5134702 (1992-07-01), Charych et al.
patent: 5142529 (1992-08-01), Parruck et al.
patent: 5172260 (1992-12-01), Takatsu
patent: 5256912 (1993-10-01), Rios
patent: 5305253 (1994-04-01), Ward
patent: 5319597 (1994-06-01), Adachi
patent: 5402425 (1995-03-01), Bladh
patent: 5461380 (1995-10-01), Peters et al.
patent: 5546401 (1996-08-01), Lee et al.
patent: 5604739 (1997-02-01), Buhrgard et al.
Arvidsson Carl-Erik
Thisell Carl-Gustaf
Hyun Soon-Dong
Nguyen Chau
Telefonaktiebolaget LM Ericsson
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