Data Transmission processing system having DMA channels running

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395842, 395858, 395864, 395 8, 395 72, 36424231, 36424232, 36424233, 364DIG1, G06F 1312, G06F 1314

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active

055309011

ABSTRACT:
A data transmission processing system provided between a host unit and peripheral devices including at least a memory device and a processing device. The host unit outputs, to the transmission processing system, DMA transmission process request commands. The data transmission process system includes a DMA control unit, provided with a plurality of DMA channels, for cyclically selecting a DMA channel from the plurality of DMA channels in accordance with a predetermined priority, the plurality of DMA channels being allocated to processes with respect to the peripheral devices, and a DMA execution unit for carrying out a DMA transmission process for transmitting data output from the host unit to the memory device via a selected DMA channel corresponding to the memory device in data transmission timing of the host unit and a DMA transmission process for transmitting data stored in the memory device to the processing device via a selected DMA channel corresponding to the processing device in accordance with the DMA transmission process request commands supplied from the host unit.

REFERENCES:
patent: 4017839 (1977-04-01), Calle et al.
patent: 4067059 (1978-01-01), Derchak
patent: 4688166 (1987-08-01), Schneider
patent: 4750107 (1988-06-01), Buggert
patent: 4831523 (1989-05-01), Lewis et al.
patent: 4933686 (1990-06-01), Izumi et al.

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