Data transmission method and arrangement

Details Data transmission method and arrangement Data transmission method and arrangement

2001-02-15

2002-09-24

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to digital conversion followed by digital to analog...

C375S345000

Reexamination Certificate

active

06456210

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a data transmission method for digital data transmission between two electric circuits in particular.
BACKGROUND OF THE INVENTION
In order to send a signal by means of a radio system transmitter, a baseband digital signal is generally converted into analogue mode using an ASIC circuit (Application Specific Integrated Circuit), whereafter the signal is converted into radio frequency mode and sent through an antenna. Correspondingly, when the radio frequency signal has been received by the antenna and converted into baseband mode, the baseband signal is generally converted into digital mode using an ASIC circuit. Consequently, the interface between the digital ASIC circuit and the analogue ASIC circuit of the transmitter and receiver of the radio system requires a larger data transmission capacity, particularly in third generation products. For example, in the WCDMA radio system (Wideband Code Division Multiple Access) data transmission employs modulation where the data to be transferred is divided into I and Q branches (in-phase and Quadrature). In such a case, both the receiver and the transmitter include separate I and Q data buses between the analogue and digital ASIC circuit. In the receiver an A/D converter of the ASIC circuit requires a six-bit bus, whose clock frequency is generally 19.2 MHz. In order to increase capacity both the I and Q branches can be connected to the same bus, but in such a case the clock frequency must be increased. In the transmitter, in turn, a D/A converter of the ASIC circuit uses ten bits. In this case too, the I and Q branch can be connected using a doubled data transmission rate (2.19.2 MHz). Thus, a 10-bit wide data bus is formed that operates at a 38.4 MHz clock frequency. The problem arising when increasing the clock frequency is, however, that the frequency band widens, and consequently the interferences become stronger. Increasing the clock frequency also adds the power consumption of the bus.
BRIEF DESCRIPTION OF THE INVENTION
It is an object of the method and the apparatus implementing the method to improve data transmission. The method according to claim
1
is thus presented as the invention.
The invention also relates to a data transmission arrangement according to claim
7
.
The preferred embodiments of the invention are disclosed in the dependent claims.
The idea of the invention is that digital data, in which bit values are based on different voltage levels, are converted into electric current. After data transmission the electric current is reconverted into the original digital data.
Several advantages are achieved with the method and arrangement of the invention. Data transmission in current form reduces interference, the number of required buses and the need to increase clock frequency. For these reasons the power consumption can also be reduced.


REFERENCES:
patent: 5113129 (1992-05-01), Hughes
patent: 5175722 (1992-12-01), Minami et al.
patent: 5548573 (1996-08-01), Takeuchi
patent: 5815107 (1998-09-01), Frankeny et al.
patent: 6128354 (2000-10-01), Rybicki et al.
patent: 6164125 (2000-12-01), Kawase et al.
English Abstract of Japanese Patent document No. JP63314928.

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